[test_rom] Make test_rom buildable for english breakfast.

This commit converts just the necessary files to DT to be able
to build the test_rom for english breakfast.

Signed-off-by: Amaury Pouly <[email protected]>

sw/device/lib/testing/BUILD

@@ -152,8 +152,8 @@ cc_library(
     hdrs = ["flash_ctrl_testutils.h"],
     target_compatible_with = [OPENTITAN_CPU],
     deps = [
-        "//hw/top_earlgrey/ip_autogen/flash_ctrl:flash_ctrl_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:flash_ctrl_c_regs",
+        "//hw/top:devicetables",
         "//sw/device/lib/base:abs_mmio",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:flash_ctrl",
@@ -318,7 +318,7 @@ cc_library(
     hdrs = ["pinmux_testutils.h"],
     target_compatible_with = [OPENTITAN_CPU],
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:devicetables",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/dif:base",
         "//sw/device/lib/dif:gpio",

sw/device/lib/testing/flash_ctrl_testutils.c

@@ -15,8 +15,11 @@
 #include "sw/device/lib/runtime/ibex.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 
-#include "flash_ctrl_regs.h"
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+#include "flash_ctrl_regs.h" // Generated
+
+#include "devicetables.h" // Generated
+
+static const dt_flash_ctrl_t *kFlashCtrlDt = &kDtFlashCtrl[0];
 
 #define MODULE_ID MAKE_MODULE_ID('f', 'c', 't')
 
@@ -300,7 +303,7 @@ status_t flash_ctrl_testutils_backdoor_init(
     dif_flash_ctrl_state_t *flash_state) {
   TRY(dif_flash_ctrl_init_state(
       flash_state,
-      mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
+      mmio_region_from_addr(dt_flash_ctrl_reg_block(kFlashCtrlDt, kDtFlashCtrlRegBlockCore))));
 
   return flash_ctrl_testutils_default_region_access(flash_state,
                                                     /*rd_en*/ true,
@@ -335,26 +338,3 @@ status_t flash_ctrl_testutils_backdoor_wait_update(const volatile uint8_t *addr,
   } while (new_data == prior_data);
   return OK_STATUS();
 }
-
-status_t flash_ctrl_testutils_show_faults(
-    const dif_flash_ctrl_state_t *flash_ctrl) {
-  dif_flash_ctrl_faults_t faults = {.memory_properties_error = false};
-  CHECK_DIF_OK(dif_flash_ctrl_get_faults(flash_ctrl, &faults));
-#define LOG_IF_FIELD_SET(_struct, _field)             \
-  if (_struct._field != 0) {                          \
-    LOG_INFO("Flash_ctrl fault status has " #_field); \
-  }
-
-  LOG_IF_FIELD_SET(faults, memory_properties_error);
-  LOG_IF_FIELD_SET(faults, read_error);
-  LOG_IF_FIELD_SET(faults, prog_window_error);
-  LOG_IF_FIELD_SET(faults, prog_type_error);
-  LOG_IF_FIELD_SET(faults, host_gnt_error);
-  LOG_IF_FIELD_SET(faults, register_integrity_error);
-  LOG_IF_FIELD_SET(faults, phy_integrity_error);
-  LOG_IF_FIELD_SET(faults, lifecycle_manager_error);
-  LOG_IF_FIELD_SET(faults, shadow_storage_error);
-#undef LOG_IF_FIELD_SET
-
-  return OK_STATUS();
-}

sw/device/lib/testing/pinmux_testutils.c

@@ -13,29 +13,22 @@
 #include "sw/device/lib/runtime/hart.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+#include "devicetables.h"
+
+static const dt_gpio_t *kGpioDt = &kDtGpio[0];
+static const dt_uart_t *kUart0Dt = &kDtUart[0];
 
 void pinmux_testutils_init(dif_pinmux_t *pinmux) {
   // Set up SW straps on IOC0-IOC2, for GPIOs 22-24
-  CHECK_DIF_OK(dif_pinmux_input_select(pinmux,
-                                       kTopEarlgreyPinmuxPeripheralInGpioGpio22,
-                                       kTopEarlgreyPinmuxInselIoc0));
-  CHECK_DIF_OK(dif_pinmux_input_select(pinmux,
-                                       kTopEarlgreyPinmuxPeripheralInGpioGpio23,
-                                       kTopEarlgreyPinmuxInselIoc1));
-  CHECK_DIF_OK(dif_pinmux_input_select(pinmux,
-                                       kTopEarlgreyPinmuxPeripheralInGpioGpio24,
-                                       kTopEarlgreyPinmuxInselIoc2));
+  CHECK_DIF_OK(dif_pinmux_mio_select_input(pinmux, dt_gpio_pin(kGpioDt, kDtGpioPinGpio22), kDtPad[kDtPadIoc0]));
+  CHECK_DIF_OK(dif_pinmux_mio_select_input(pinmux, dt_gpio_pin(kGpioDt, kDtGpioPinGpio23), kDtPad[kDtPadIoc1]));
+  CHECK_DIF_OK(dif_pinmux_mio_select_input(pinmux, dt_gpio_pin(kGpioDt, kDtGpioPinGpio24), kDtPad[kDtPadIoc2]));
 
   // Configure UART0 RX input to connect to MIO pad IOC3
-  CHECK_DIF_OK(dif_pinmux_input_select(pinmux,
-                                       kTopEarlgreyPinmuxPeripheralInUart0Rx,
-                                       kTopEarlgreyPinmuxInselIoc3));
-  CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIoc3,
-                                        kTopEarlgreyPinmuxOutselConstantHighZ));
+  CHECK_DIF_OK(dif_pinmux_mio_select_input(pinmux, dt_uart_pin(kUart0Dt, kDtUartPinRx), kDtPad[kDtPadIoc3]));
+  CHECK_DIF_OK(dif_pinmux_mio_select_output(pinmux, kDtPad[kDtPadIoc3], kDtPinConstantHighZ));
   // Configure UART0 TX output to connect to MIO pad IOC4
-  CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIoc4,
-                                        kTopEarlgreyPinmuxOutselUart0Tx));
+  CHECK_DIF_OK(dif_pinmux_mio_select_output(pinmux, kDtPad[kDtPadIoc4], dt_uart_pin(kUart0Dt, kDtUartPinTx)));
 
 #if !OT_IS_ENGLISH_BREAKFAST
   // Enable pull-ups on UART0 RX
@@ -89,10 +82,11 @@ void pinmux_testutils_init(dif_pinmux_t *pinmux) {
 #endif
 
   // Configure USBDEV SENSE outputs to be high-Z (IOC7)
-  CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIoc7,
-                                        kTopEarlgreyPinmuxOutselConstantHighZ));
+  CHECK_DIF_OK(dif_pinmux_mio_select_output(pinmux, kDtPad[kDtPadIoc7], kDtPinConstantHighZ));
 }
 
+// FIXME convert to DT
+#ifndef OT_IS_ENGLISH_BREAKFAST
 // Mapping of Chip IOs to the GPIO peripheral.
 //
 // Depending on the simulation platform, there may be a limitation to how chip
@@ -138,6 +132,7 @@ const dif_pinmux_index_t kPinmuxTestutilsGpioMioOutPins[kDifGpioNumPins] = {
     kTopEarlgreyPinmuxMioOutIor6,  kTopEarlgreyPinmuxMioOutIor7,
     kTopEarlgreyPinmuxMioOutIor10, kTopEarlgreyPinmuxMioOutIor11,
     kTopEarlgreyPinmuxMioOutIor12, kTopEarlgreyPinmuxMioOutIor13};
+#endif
 
 uint32_t pinmux_testutils_get_testable_gpios_mask(void) {
   switch (kDeviceType) {
@@ -159,7 +154,7 @@ uint32_t pinmux_testutils_get_testable_gpios_mask(void) {
 
 uint32_t pinmux_testutils_read_strap_pin(dif_pinmux_t *pinmux, dif_gpio_t *gpio,
                                          dif_gpio_pin_t io,
-                                         top_earlgrey_muxed_pads_t pad) {
+                                         dt_pinmux_muxed_pad_t pad) {
   // Turn off the pull enable on the pad and read the IO.
   dif_pinmux_pad_attr_t attr = {.flags = 0};
   dif_pinmux_pad_attr_t attr_out;
@@ -193,12 +188,12 @@ uint32_t pinmux_testutils_read_strap_pin(dif_pinmux_t *pinmux, dif_gpio_t *gpio,
 uint32_t pinmux_testutils_read_straps(dif_pinmux_t *pinmux, dif_gpio_t *gpio) {
   uint32_t strap = 0;
   strap |= pinmux_testutils_read_strap_pin(pinmux, gpio, 22,
-                                           kTopEarlgreyMuxedPadsIoc0);
+                                           dt_pad_mio_pad(kDtPad[kDtPadIoc0]));
   strap |= pinmux_testutils_read_strap_pin(pinmux, gpio, 23,
-                                           kTopEarlgreyMuxedPadsIoc1)
+                                           dt_pad_mio_pad(kDtPad[kDtPadIoc1]))
            << 2;
   strap |= pinmux_testutils_read_strap_pin(pinmux, gpio, 24,
-                                           kTopEarlgreyMuxedPadsIoc2)
+                                           dt_pad_mio_pad(kDtPad[kDtPadIoc2]))
            << 4;
   return strap;
 }

sw/device/lib/testing/pinmux_testutils.h

@@ -11,22 +11,22 @@
 #include "sw/device/lib/dif/dif_gpio.h"
 #include "sw/device/lib/dif/dif_pinmux.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+#include "devicetables.h"
 
 /**
  * Define a pinmux configuration for a peripheral input and output .
  */
 typedef struct pinmux_testutils_peripheral_pin {
-  top_earlgrey_pinmux_peripheral_in_t peripheral_in;
-  top_earlgrey_pinmux_outsel_t outsel;
+  dt_pinmux_peripheral_in_t peripheral_in;
+  dt_pinmux_outsel_t outsel;
 } pinmux_testutils_peripheral_pin_t;
 
 /**
  * Define a pinmux configuration for a mio input and output.
  */
 typedef struct pinmux_testutils_mio_pin {
-  top_earlgrey_pinmux_mio_out_t mio_out;
-  top_earlgrey_pinmux_insel_t insel;
+  dt_pinmux_mio_out_t mio_out;
+  dt_pinmux_insel_t insel;
 } pinmux_testutils_mio_pin_t;
 
 /**
@@ -74,7 +74,7 @@ uint32_t pinmux_testutils_get_testable_gpios_mask(void);
  */
 uint32_t pinmux_testutils_read_strap_pin(dif_pinmux_t *pinmux, dif_gpio_t *gpio,
                                          dif_gpio_pin_t io,
-                                         top_earlgrey_muxed_pads_t pad);
+                                         dt_pinmux_muxed_pad_t pad);
 
 /**
  * Reads the OpenTitan sw strap pins for the strap configuration value.

sw/device/lib/testing/test_rom/BUILD

@@ -32,8 +32,11 @@ opentitan_binary(
         "//hw/top_earlgrey:fpga_cw305",
         "//hw/top_earlgrey:fpga_cw340",
         "//hw/top_earlgrey:sim_dv_base",
-        "//hw/top_earlgrey:sim_verilator_base",
-    ],
+    ] +
+    select({
+        "//sw/device:is_english_breakfast": ["//hw/top_englishbreakfast:sim_verilator_base"],
+        "//conditions:default": ["//hw/top_earlgrey:sim_verilator_base"],
+    }),
     kind = "rom",
     linker_script = ":linker_script",
     deps = [

sw/device/lib/testing/test_rom/english_breakfast_fake_driver_funcs.c

@@ -29,6 +29,10 @@ dif_result_t dif_rstmgr_init(mmio_region_t base_addr, dif_rstmgr_t *rstmgr) {
   return kDifOk;
 }
 
+dif_result_t dif_rstmgr_init_from_dt(const dt_rstmgr_t *dt, dif_rstmgr_t *rstmgr) {
+  return kDifOk;
+}
+
 dif_result_t dif_rstmgr_reset_info_get(const dif_rstmgr_t *handle,
                                        dif_rstmgr_reset_info_bitfield_t *info) {
   *info = 1 << kRstmgrReasonPowerOn;

sw/device/lib/testing/test_rom/test_rom.c

@@ -23,15 +23,22 @@
 #include "sw/device/lib/testing/test_framework/status.h"
 #include "sw/device/silicon_creator/lib/base/sec_mmio.h"
 #include "sw/device/silicon_creator/lib/chip_info.h"
+#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h"
 #if !OT_IS_ENGLISH_BREAKFAST
 #include "sw/device/silicon_creator/lib/drivers/retention_sram.h"
 #endif
 #include "sw/device/silicon_creator/lib/manifest.h"
 #include "sw/device/silicon_creator/rom/bootstrap.h"
 
 #include "flash_ctrl_regs.h"
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"  // Generated.
 #include "otp_ctrl_regs.h"
+#include "devicetables.h"
+
+static const dt_pinmux_t *kPinmuxDt = &kDtPinmux[0];
+static const dt_rstmgr_t *kRstmgrDt = &kDtRstmgr[0];
+static const dt_flash_ctrl_t *kFlashCtrlDt = &kDtFlashCtrl[0];
+static const dt_uart_t *kUart0Dt = &kDtUart[0];
+static const dt_rv_core_ibex_t *kRvCoreIbexDt = &kDtRvCoreIbex[0];
 
 /* These symbols are defined in
  * `opentitan/sw/device/lib/testing/test_rom/test_rom.ld`, and describes the
@@ -99,17 +106,15 @@ bool rom_test_main(void) {
   sec_mmio_init();
 
   // Configure the pinmux.
-  CHECK_DIF_OK(dif_pinmux_init(
-      mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR), &pinmux));
+  CHECK_DIF_OK(dif_pinmux_init_from_dt(kPinmuxDt, &pinmux));
   pinmux_testutils_init(&pinmux);
 
-  CHECK_DIF_OK(dif_rstmgr_init(
-      mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
+  CHECK_DIF_OK(dif_rstmgr_init_from_dt(kRstmgrDt, &rstmgr));
 
   // Initialize the flash.
   CHECK_DIF_OK(dif_flash_ctrl_init_state(
       &flash_ctrl,
-      mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
+      mmio_region_from_addr(dt_flash_ctrl_reg_block(kFlashCtrlDt, kDtFlashCtrlRegBlockCore))));
   CHECK_DIF_OK(dif_flash_ctrl_start_controller_init(&flash_ctrl));
   CHECK_STATUS_OK(flash_ctrl_testutils_wait_for_init(&flash_ctrl));
 #if !OT_IS_ENGLISH_BREAKFAST
@@ -136,8 +141,7 @@ bool rom_test_main(void) {
 
   // Setup the UART for printing messages to the console.
   if (kDeviceType != kDeviceSimDV) {
-    CHECK_DIF_OK(dif_uart_init(
-        mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR), &uart0));
+    CHECK_DIF_OK(dif_uart_init_from_dt(kUart0Dt, &uart0));
     CHECK(kUartBaudrate <= UINT32_MAX, "kUartBaudrate must fit in uint32_t");
     CHECK(kClockFreqPeripheralHz <= UINT32_MAX,
           "kClockFreqPeripheralHz must fit in uint32_t");
@@ -176,8 +180,7 @@ bool rom_test_main(void) {
   // Print the FPGA version-id.
   // This is guaranteed to be zero on all non-FPGA implementations.
   dif_rv_core_ibex_fpga_info_t fpga;
-  CHECK_DIF_OK(dif_rv_core_ibex_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR), &ibex));
+  CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kRvCoreIbexDt, &ibex));
   CHECK_DIF_OK(dif_rv_core_ibex_read_fpga_info(&ibex, &fpga));
   if (fpga != 0) {
     LOG_INFO("TestROM:%08x", fpga);
@@ -201,7 +204,7 @@ bool rom_test_main(void) {
 
   // Always select slot a and enable address translation if manifest says to.
   const manifest_t *manifest =
-      (const manifest_t *)TOP_EARLGREY_EFLASH_BASE_ADDR;
+      (const manifest_t *)dt_flash_ctrl_reg_block(kFlashCtrlDt, kDtFlashCtrlRegBlockMem);
   uintptr_t entry_point = manifest_entry_point_get(manifest);
   if (manifest->address_translation == kHardenedBoolTrue) {
     dif_rv_core_ibex_addr_translation_mapping_t addr_map = {

sw/device/lib/testing/test_rom/test_rom_start.S

@@ -2,7 +2,6 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/multibits_asm.h"
 #include "ast_regs.h"
@@ -14,6 +13,20 @@
 #include "sensor_ctrl_regs.h"
 #include "sram_ctrl_regs.h"
 
+#ifndef OT_IS_ENGLISH_BREAKFAST
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h"
+#define OTP_CTRL_CORE_BASE_ADDR   TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR
+#define AST_BASE_ADDR             TOP_EARLGREY_AST_BASE_ADDR
+#define CLKMGR_AON_BASE_ADDR      TOP_EARLGREY_CLKMGR_AON_BASE_ADDR
+#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR
+#else
+#include "hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h"
+#define OTP_CTRL_CORE_BASE_ADDR   TOP_ENGLISHBREAKFAST_OTP_CTRL_CORE_BASE_ADDR
+#define AST_BASE_ADDR             TOP_ENGLISHBREAKFAST_AST_BASE_ADDR
+#define CLKMGR_AON_BASE_ADDR      TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR
+#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR
+#endif
+
 /**
  * Test ROM interrupt vectors.
  *
@@ -148,16 +161,16 @@ _reset_start:
 _start:
 #if !OT_IS_ENGLISH_BREAKFAST
   // Check if AST initialization should be skipped.
-  li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
+  li   a0, (OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_OFFSET(a0)
   li   t1, MULTIBIT_ASM_BOOL4_TRUE
   bne  t0, t1, .L_ast_init_skip
 
   // Copy the AST configuration from OTP.
-  li   a0, (TOP_EARLGREY_AST_BASE_ADDR)
-  li   a1, (TOP_EARLGREY_AST_BASE_ADDR + AST_REGAL_REG_OFFSET + 4)
-  li   a2, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
+  li   a0, (AST_BASE_ADDR)
+  li   a1, (AST_BASE_ADDR + AST_REGAL_REG_OFFSET + 4)
+  li   a2, (OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + \
             OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET)
   call crt_section_copy
@@ -171,10 +184,10 @@ _start:
   beqz t0, .L_ast_done_loop
 
   // Enable jittery clock if enabled in OTP.
-  li   a0, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
+  li   a0, (OTP_CTRL_CORE_BASE_ADDR + \
             OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET)
   lw   t0, OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET(a0)
-  li   a0, TOP_EARLGREY_CLKMGR_AON_BASE_ADDR
+  li   a0, CLKMGR_AON_BASE_ADDR
   sw   t0, CLKMGR_JITTER_ENABLE_REG_OFFSET(a0)
 
 .L_ast_init_skip:
@@ -228,7 +241,7 @@ _start:
   // this to optimize test run times.
   lw    t0, kDeviceType
   beqz  t0, .L_sram_init_skip
-  li    a0, TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR
+  li    a0, SRAM_CTRL_MAIN_REGS_BASE_ADDR
   li    t0, (1 << SRAM_CTRL_CTRL_INIT_BIT)
   sw    t0, SRAM_CTRL_CTRL_REG_OFFSET(a0)
 

sw/device/silicon_creator/lib/drivers/BUILD

@@ -259,7 +259,7 @@ dual_cc_library(
     deps = dual_inputs(
         shared = [
             "//hw/ip/rv_core_ibex/data:rv_core_ibex_c_regs",
-            "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+            "//hw/top:devicetables",
             "//sw/device/lib/arch:device",
             "//sw/device/lib/base:abs_mmio",
             "//sw/device/lib/base:csr",
@@ -719,8 +719,8 @@ cc_library(
     hdrs = ["uart.h"],
     deps = [
         ":ibex",
+        "//hw/top:devicetables",
         "//hw/ip/uart/data:uart_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:abs_mmio",
         "//sw/device/lib/base:bitfield",