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o1vm/riscv32i: define registers #2743

Merged
merged 3 commits into from
Nov 14, 2024

o1vm/riscv32i: use a var for nb of GP registers + index traits

d248253
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Merged

o1vm/riscv32i: define registers #2743

o1vm/riscv32i: use a var for nb of GP registers + index traits
d248253
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Codecov / codecov/project failed Nov 4, 2024 in 0s

73.68% (-0.03%) compared to 0f96782

View this Pull Request on Codecov

73.68% (-0.03%) compared to 0f96782

Details

Codecov Report

Attention: Patch coverage is 0% with 23 lines in your changes missing coverage. Please review.

Project coverage is 73.68%. Comparing base (0f96782) to head (d248253).

Files with missing lines Patch % Lines
o1vm/src/interpreters/riscv32i/registers.rs 0.00% 23 Missing ⚠️
Additional details and impacted files
@@                      Coverage Diff                       @@
##           dw/update-o1vm-description    #2743      +/-   ##
==============================================================
- Coverage                       73.70%   73.68%   -0.03%     
==============================================================
  Files                             249      250       +1     
  Lines                           57866    57889      +23     
==============================================================
+ Hits                            42650    42654       +4     
- Misses                          15216    15235      +19     

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