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Source code formatting
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@rpls
rpls committed Feb 20, 2021
1 parent 9fe145c commit 59b1974
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9 changes: 6 additions & 3 deletions .scalafmt.conf
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version = "2.3.2"
align = more
version = 2.7.5
maxColumn = 100
align.preset = more
align.multiline = false
newlines.source = keep
danglingParentheses.callSite = false
continuationIndent.callSite = 2
continuationIndent.defnSite = 2
continuationIndent.extendSite = 0
verticalMultiline.arityThreshold = 4
verticalMultiline.newlineAfterOpenParen = true

1 change: 1 addition & 0 deletions project/plugins.sbt
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addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.2")
181 changes: 91 additions & 90 deletions src/main/scala/mupq/IceBlackbox.scala
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Expand Up @@ -2,66 +2,69 @@ package mupq

import spinal.core._

/**
* BlackBox model for the PLL present in Ice40 FPGAs.
/** BlackBox model for the PLL present in Ice40 FPGAs.
*/
class Ice40PLLPad(divF: Int, divR: Int, divQ: Int) extends BlackBox {
val generic = new Generic {
val FEEDBACK_PATH = "SIMPLE"
val FEEDBACK_PATH = "SIMPLE"
val DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"
val DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"
val PLLOUT_SELECT = "GENCLK"
val FDA_FEEDBACK = B(0xF, 4 bits)
val FDA_RELATIVE = B(0xF, 4 bits)
val DIVF = B(divF, 7 bits)
val DIVR = B(divR, 4 bits)
val DIVQ = B(divQ, 3 bits)
val FILTER_RANGE = B(0x2, 3 bits)
val PLLOUT_SELECT = "GENCLK"
val FDA_FEEDBACK = B(0xf, 4 bits)
val FDA_RELATIVE = B(0xf, 4 bits)
val DIVF = B(divF, 7 bits)
val DIVR = B(divR, 4 bits)
val DIVQ = B(divQ, 3 bits)
val FILTER_RANGE = B(0x2, 3 bits)
}
val io = new Bundle {
val RESETB = in Bool
val BYPASS = in Bool
val PACKAGEPIN = in Bool
val RESETB = in Bool
val BYPASS = in Bool
val PACKAGEPIN = in Bool
val PLLOUTGLOBAL = out Bool
val LOCK = out Bool
val LOCK = out Bool
}
noIoPrefix()
setBlackBoxName("SB_PLL40_PAD")
}

class Ice40PLL2FCore(
divF: Int, divR: Int, divQ: Int
) extends BlackBox {
divF: Int,
divR: Int,
divQ: Int
)
extends BlackBox {
val generic = new Generic {
val FEEDBACK_PATH = "PHASE_AND_DELAY"
val FEEDBACK_PATH = "PHASE_AND_DELAY"
val DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"
val DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"
val PLLOUT_SELECT_PORTA = "SHIFTREG_0deg"
val PLLOUT_SELECT_PORTB = "SHIFTREG_90deg"
val SHIFTREG_DIV_MODE = False
val FDA_FEEDBACK = B(0xF, 4 bits)
val FDA_RELATIVE = B(0xF, 4 bits)
val DIVF = B(divF, 7 bits)
val DIVR = B(divR, 4 bits)
val DIVQ = B(divQ, 3 bits)
val FILTER_RANGE = B(0x7, 3 bits)
val PLLOUT_SELECT_PORTA = "SHIFTREG_0deg"
val PLLOUT_SELECT_PORTB = "SHIFTREG_90deg"
val SHIFTREG_DIV_MODE = False
val FDA_FEEDBACK = B(0xf, 4 bits)
val FDA_RELATIVE = B(0xf, 4 bits)
val DIVF = B(divF, 7 bits)
val DIVR = B(divR, 4 bits)
val DIVQ = B(divQ, 3 bits)
val FILTER_RANGE = B(0x7, 3 bits)
}
val io = new Bundle {
val RESETB = in Bool
val BYPASS = in Bool
val REFERENCECLK = in Bool
val RESETB = in Bool
val BYPASS = in Bool
val REFERENCECLK = in Bool
val PLLOUTGLOBALA = out Bool
val PLLOUTGLOBALB = out Bool
val LOCK = out Bool
val LOCK = out Bool
}
noIoPrefix()
setBlackBoxName("SB_PLL40_2F_CORE")
}

class Ice40IO(pinType: Int = 0, pullup: Boolean = false, negTrigger: Boolean = false) extends BlackBox {
class Ice40IO(pinType: Int = 0, pullup: Boolean = false, negTrigger: Boolean = false)
extends BlackBox {
val generic = new Generic {
val PIN_TYPE = B(pinType, 6 bits)
val PULLUP = if (pullup) True else False
val PULLUP = if (pullup) True else False
// val NEG_TRIGGER = if (negTrigger) True else False
// val IO_STANDARD = "SB_LVCMOS"
}
Expand All @@ -72,7 +75,7 @@ class Ice40IO(pinType: Int = 0, pullup: Boolean = false, negTrigger: Boolean = f
// val INPUT_CLK = in Bool
// val OUTPUT_CLK = in Bool
val OUTPUT_ENABLE = in Bool
val D_OUT_0 = in Bool
val D_OUT_0 = in Bool
// val D_OUT_1 = in Bool
val D_IN_0 = out Bool
// val D_IN_1 = out Bool
Expand All @@ -81,80 +84,78 @@ class Ice40IO(pinType: Int = 0, pullup: Boolean = false, negTrigger: Boolean = f
setBlackBoxName("SB_IO")
}

/**
* BlackBox model for the large SPRAM blocks of Ice40 UltraPlus FPGAs.
/** BlackBox model for the large SPRAM blocks of Ice40 UltraPlus FPGAs.
*/
class Ice40SPRAM extends BlackBox {
val io = new Bundle {
val ADDRESS = in Bits (14 bits)
val DATAIN = in Bits (16 bits)
val DATAOUT = out Bits (16 bits)
val MASKWREN = in Bits (4 bits)
val WREN = in Bool
val ADDRESS = in Bits (14 bits)
val DATAIN = in Bits (16 bits)
val DATAOUT = out Bits (16 bits)
val MASKWREN = in Bits (4 bits)
val WREN = in Bool
val CHIPSELECT = in Bool
val CLOCK = in Bool
val STANDBY = in Bool
val SLEEP = in Bool
val POWEROFF = in Bool
val CLOCK = in Bool
val STANDBY = in Bool
val SLEEP = in Bool
val POWEROFF = in Bool
}
noIoPrefix()
mapClockDomain(clock = io.CLOCK)
setBlackBoxName("SB_SPRAM256KA")
}

/**
* BlackBox Model for DSA
/** BlackBox Model for DSA
*/
class Ice40Multiplier(registerOutput : Boolean = false) extends BlackBox {
class Ice40Multiplier(registerOutput: Boolean = false) extends BlackBox {
val generics = new Generic {
val A_REG = B"0"
val B_REG = B"0"
val C_REG = B"0"
val D_REG = B"0"
val TOP_8X8_MULT_REG = B"0"
val BOT_8X8_MULT_REG = B"0"
val A_REG = B"0"
val B_REG = B"0"
val C_REG = B"0"
val D_REG = B"0"
val TOP_8X8_MULT_REG = B"0"
val BOT_8X8_MULT_REG = B"0"
val PIPELINE_16X16_MULT_REG1 = B"0"
val PIPELINE_16X16_MULT_REG2 = if (registerOutput) B"1" else B"0"
val TOPOUTPUT_SELECT = B"11"
val TOPADDSUB_LOWERINPUT = B"00"
val TOPADDSUB_UPPERINPUT = B"0"
val TOPADDSUB_CARRYSELECT = B"00"
val BOTOUTPUT_SELECT = B"11"
val BOTADDSUB_LOWERINPUT = B"00"
val BOTADDSUB_UPPERINPUT = B"0"
val BOTADDSUB_CARRYSELECT = B"00"
val MODE_8X8 = B"0"
val A_SIGNED = B"0"
val B_SIGNED = B"0"
val TOPOUTPUT_SELECT = B"11"
val TOPADDSUB_LOWERINPUT = B"00"
val TOPADDSUB_UPPERINPUT = B"0"
val TOPADDSUB_CARRYSELECT = B"00"
val BOTOUTPUT_SELECT = B"11"
val BOTADDSUB_LOWERINPUT = B"00"
val BOTADDSUB_UPPERINPUT = B"0"
val BOTADDSUB_CARRYSELECT = B"00"
val MODE_8X8 = B"0"
val A_SIGNED = B"0"
val B_SIGNED = B"0"
}

val io = new Bundle {
val CLK = in Bool
val CE = in Bool
val A = in Bits(16 bits)
val AHOLD = in Bool
val B = in Bits(16 bits)
val BHOLD = in Bool
val C = in Bits(16 bits)
val CHOLD = in Bool
val D = in Bits(16 bits)
val DHOLD = in Bool
val IRSTTOP = in Bool
val ORSTTOP = in Bool
val OLOADTOP = in Bool
val ADDSUBTOP = in Bool
val OHOLDTOP = in Bool
val O = out Bits(32 bits)
val IRSTBOT = in Bool
val ORSTBOT = in Bool
val OLOADBOT = in Bool
val ADDSUBBOT = in Bool
val OHOLDBOT = in Bool
val CI = in Bool
val CO = out Bool
val ACCUMCI = in Bool
val ACCUMCO = out Bool
val SIGNEXTIN = in Bool
val CLK = in Bool
val CE = in Bool
val A = in Bits (16 bits)
val AHOLD = in Bool
val B = in Bits (16 bits)
val BHOLD = in Bool
val C = in Bits (16 bits)
val CHOLD = in Bool
val D = in Bits (16 bits)
val DHOLD = in Bool
val IRSTTOP = in Bool
val ORSTTOP = in Bool
val OLOADTOP = in Bool
val ADDSUBTOP = in Bool
val OHOLDTOP = in Bool
val O = out Bits (32 bits)
val IRSTBOT = in Bool
val ORSTBOT = in Bool
val OLOADBOT = in Bool
val ADDSUBBOT = in Bool
val OHOLDBOT = in Bool
val CI = in Bool
val CO = out Bool
val ACCUMCI = in Bool
val ACCUMCO = out Bool
val SIGNEXTIN = in Bool
val SIGNEXTOUT = out Bool
}
noIoPrefix()
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