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Multi Cycle/Alu.v

@@ -0,0 +1,42 @@
+`define add 3'b000
+`define sub 3'b001
+`define And 3'b010
+`define Or 3'b011
+`define Xor 3'b100
+`define slt 3'b101
+`define sltu 3'b110
+
+module Alu(A, B, opc, neg, zero, result);
+	input [31:0] A, B;
+	input [2:0] opc;
+	output neg, zero;
+	output reg [31:0] result;
+
+	always@(A, B, opc)begin
+		result = 32'd0;
+		case(opc)
+		`add: result = A + B;
+		`sub: result = A - B;
+		`And: result = A & B;
+		`Or: result = A | B;	
+		`Xor: result = A ^ B;
+		`slt: result = (A[31] > B[31]) ? 1 :
+				(A[31] < B[31]) ? 0 :
+				(A[31] == 1) ? ((A > B) ? 1 : 0) :
+				(A[31] == 0) ? ((A < B) ? 1 : 0) : 0 ;
+		`sltu: result = (A < B) ? 1 : 0;
+		default: result = 32'd0;
+		endcase
+	end
+
+	assign zero = (result == 0) ? 1 : 0;
+	assign neg = result[31];
+endmodule
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Multi Cycle/AluControl.v

@@ -0,0 +1,44 @@
+`define add 2'b00
+`define sub 2'b01
+`define ch_f 2'b10
+
+module AluControl(AluOp, func3, func7, AluC);
+
+	input [1:0] AluOp;
+	input [2:0] func3;
+	input [6:0] func7;
+	output reg [2:0] AluC;
+
+	wire [9:0] mode;
+	assign mode = {func7, func3};
+	always@(AluOp, func3, func7)begin
+		AluC = 3'b000;
+		case(AluOp)
+		`add: AluC = 3'b000;
+		`sub: AluC = 3'b001;
+		`ch_f: AluC = (mode == 0) ? 3'b000 :
+				(mode == 256) ? 3'b001 :
+				(mode == 7) ? 3'b010 :
+				(mode == 6) ? 3'b011 :
+				(mode == 2) ? 3'b101 :
+				(mode == 3) ? 3'b110 :
+				(func3 == 0) ? 3'b000 :
+				(func3 == 4) ? 3'b100 :
+				(func3 == 6) ? 3'b011 :
+				(func3 == 2) ? 3'b101 :
+				(func3 == 3) ? 3'b110 : 3'b000;
+		endcase
+	end
+endmodule
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Multi Cycle/Branch_cntr.v

@@ -0,0 +1,20 @@
+`define beq 3'd0
+`define bne 3'd1
+`define blt 3'd4
+`define bge 3'd5
+
+module Branch_cntr(func3, sel);
+	input [2:0] func3;
+	output reg [1:0] sel;
+
+	always@(func3)begin
+		sel = 2'b0;
+		case(func3)
+		`beq: sel = 2'b00;
+		`bne: sel = 2'b01;
+		`blt: sel = 2'b10;
+		`bge: sel = 2'b11;
+		default: sel = 2'b00;
+		endcase
+	end
+endmodule

Multi Cycle/ImmExt_unit.v

@@ -0,0 +1,17 @@
+module ImmExt_unit (instruction, ImmSrc, ImmExt);
+    input [31:0] instruction;
+    input [2:0] ImmSrc;
+    output reg [31:0] ImmExt;
+
+    always @(instruction, ImmSrc) begin
+        case (ImmSrc)
+            3'd0: ImmExt={{20{instruction[31]}},instruction[31:20]}; //I type
+            3'd1: ImmExt={{20{instruction[31]}},instruction[31:25],instruction[11:7]}; //S type
+            3'd2: ImmExt={{19{instruction[31]}},instruction[31],instruction[7],instruction[30:25],instruction[11:8],1'b0}; //B type
+       	    3'd3: ImmExt={{11{instruction[31]}},instruction[31],instruction[19:12],instruction[20],instruction[30:21],1'b0}; //J type
+	    3'd4: ImmExt={instruction[31:12],12'd0}; //U type
+            default: ImmExt =32'd0; 
+        endcase
+    end
+
+endmodule