Get registers working.

examples/hello.vir

@@ -1,19 +1,24 @@
 pub mod Top {
     incoming clk : Clock;
     incoming reset : Word[1];
-    outgoing out : Word[1];
+    outgoing out : Word[3];
 
-    out := reset;
+    out := buffer.out;
 
-    mod foo of Foo;
-    foo.in := reset;
+    reg counter : Word[3] on clk;
+    counter <= if reset { 0 } else { counter->add(1) };
+
+    mod buffer of Buffer;
+    buffer.clk := clk;
+    buffer.in := counter;
 }
 
-mod Foo {
-    incoming in : Word[1];
-    incoming out : Word[1];
+mod Buffer {
+    incoming clk : Clock;
+    incoming in : Word[3];
+    outgoing out : Word[3];
 
-    node tmp : Word[1];
-    tmp := in;
-    out := tmp;
+    reg buffer : Word[3] on clk;
+    buffer <= in;
+    out := buffer;
 }

src/verilog.rs

@@ -111,12 +111,9 @@ impl<'a> Verilog<'a> {
             SimpleComponentKind::Reg => {
                 let expr = self.db.moddef_typecheck_wire(moddef.clone(), component.clone().as_path())?;
                 let typ = expr.typ();
-                let width_str = make_width_str(self.db, typ);
-                let clk: String = todo!();
-                //let clock_ssa = self.verilog_expr(clk)?;
-                let connect_ssa = self.verilog_expr(expr)?;
-                let width = if let Type::Word(n) = expr.typ() { n } else { panic!() };
-                let max_bit = width - 1;
+                let clk = component_ast.clock.unwrap();
+                let connect_ssa = self.verilog_expr(expr.clone())?;
+                let width_str = make_width_str(self.db, typ.clone());
                 writeln!(self.writer, "    reg  {width_str} {component};")?;
                 writeln!(self.writer, "    always @(posedge {clk}) begin")?;
                 writeln!(self.writer, "        {component} <= {connect_ssa};")?;