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cargo_test.yaml
144 workflow runs
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Work on item resolution, even across imports. Run cargo test #69: Commit 9b1ccbf pushed by mmaloney-sf
July 14, 2024 06:46 50s master
master
July 14, 2024 06:46 50s
Trying out cleaner design for the Salsa Db in phase.rs. Run cargo test #68: Commit 40a8b7e pushed by mmaloney-sf
July 14, 2024 02:45 47s master
master
July 14, 2024 02:45 47s
Add import statement syntax. Run cargo test #67: Commit bc7949a pushed by mmaloney-sf
July 14, 2024 01:40 51s master
master
July 14, 2024 01:40 51s
Add gcd example. Run cargo test #66: Commit 18a51ba pushed by mmaloney-sf
July 12, 2024 16:32 48s master
master
July 12, 2024 16:32 48s
Properly set up the contexts for match arms. Run cargo test #65: Commit fbcf527 pushed by mmaloney-sf
July 12, 2024 16:05 1m 3s master
master
July 12, 2024 16:05 1m 3s
Add TypedPat for tracking type information down a match statement. Run cargo test #64: Commit 6e093ba pushed by mmaloney-sf
July 12, 2024 15:39 47s master
master
July 12, 2024 15:39 47s
Progress on match statements. Run cargo test #63: Commit c27ca3b pushed by mmaloney-sf
July 12, 2024 05:26 45s master
master
July 12, 2024 05:26 45s
Kinda get match statements to work. Run cargo test #62: Commit f576b49 pushed by mmaloney-sf
July 12, 2024 03:44 45s master
master
July 12, 2024 03:44 45s
Add context parameter to typechecking to support local bindings. Run cargo test #61: Commit f00d242 pushed by mmaloney-sf
July 11, 2024 22:23 48s master
master
July 11, 2024 22:23 48s
Add parsing and partial typechecking for match exprs. Run cargo test #60: Commit 0b605e3 pushed by mmaloney-sf
July 11, 2024 22:11 49s master
master
July 11, 2024 22:11 49s
Verilog pretty printing. Run cargo test #59: Commit d3b834b pushed by mmaloney-sf
July 11, 2024 21:08 48s master
master
July 11, 2024 21:08 48s
Properly set the tag bits of an alt type. Run cargo test #58: Commit 7a21f76 pushed by mmaloney-sf
July 11, 2024 20:58 45s master
master
July 11, 2024 20:58 45s
Some work towards alt types. Run cargo test #57: Commit 350a5b6 pushed by mmaloney-sf
July 11, 2024 20:28 43s master
master
July 11, 2024 20:28 43s
Add index ranges, inc() method. Run cargo test #56: Commit c87dd7b pushed by mmaloney-sf
July 11, 2024 18:58 45s master
master
July 11, 2024 18:58 45s
Add typechecking for indexing and for boolean operators. Run cargo test #55: Commit bfd4685 pushed by mmaloney-sf
July 11, 2024 15:18 51s master
master
July 11, 2024 15:18 51s
Get registers working. Run cargo test #54: Commit 034eb04 pushed by mmaloney-sf
July 8, 2024 17:19 49s master
master
July 8, 2024 17:19 49s
Remove some deadcode in sim. Run cargo test #53: Commit 5335eec pushed by mmaloney-sf
May 23, 2024 05:04 43s master
master
May 23, 2024 05:04 43s
Add some basic syntax for ports. Run cargo test #52: Commit 09ce265 pushed by mmaloney-sf
May 22, 2024 01:14 50s master
master
May 22, 2024 01:14 50s
Verilog output. Run cargo test #51: Commit 16cda70 pushed by mmaloney-sf
May 13, 2024 15:08 48s master
master
May 13, 2024 15:08 48s
Add if expressions. Run cargo test #50: Commit 04c8a68 pushed by mmaloney-sf
May 12, 2024 02:39 51s master
master
May 12, 2024 02:39 51s
Woops. Run cargo test #49: Commit 838a270 pushed by mmaloney-sf
May 11, 2024 19:18 47s master
master
May 11, 2024 19:18 47s
Progress. Run cargo test #48: Commit b132817 pushed by mmaloney-sf
May 11, 2024 06:10 35s master
master
May 11, 2024 06:10 35s
Add UartSender example. Run cargo test #47: Commit 4f327c9 pushed by mmaloney-sf
May 11, 2024 00:14 45s master
master
May 11, 2024 00:14 45s
Don't panic when a component isn't connected. Run cargo test #46: Commit 500a2e7 pushed by mmaloney-sf
May 10, 2024 23:15 46s master
master
May 10, 2024 23:15 46s
Got simulation with submodules to work. Run cargo test #45: Commit e67ebdf pushed by mmaloney-sf
May 10, 2024 17:40 45s master
master
May 10, 2024 17:40 45s