Add .tool-versions file and .core file, clean up print statements

midimaster21b · Nov 5, 2022 · d6c2222 · d6c2222
1 parent 186939f
commit d6c2222
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Showing 5 changed files with 40 additions and 7 deletions.
diff --git a/.tool-versions b/.tool-versions
@@ -0,0 +1 @@
+python 3.9.7
diff --git a/i2c_bfm.core b/i2c_bfm.core
@@ -0,0 +1,31 @@
+CAPI=2:
+name: midimaster21b:bfm:i2c:0.1.0
+description: A basic i2c BFM
+
+filesets:
+  rtl:
+    files:
+      - src/rtl/i2c_slave_bfm.sv
+      - src/rtl/i2c_master_bfm.sv
+    file_type: systemVerilogSource
+
+  tb:
+    files:
+      - src/tb/i2c_tb.sv
+    file_type: systemVerilogSource
+
+targets:
+  # Special FuseSoC target
+  default: &default
+    default_tool: vivado
+    filesets:
+      - rtl
+
+  # Simulation target
+  sim:
+    <<: *default
+    description: Simulate the design
+    default_tool: xsim
+    filesets_append:
+      - tb
+    toplevel: i2c_tb
diff --git a/src/rtl/i2c_master_bfm.sv b/src/rtl/i2c_master_bfm.sv
@@ -135,7 +135,7 @@ module i2c_master_bfm(scl, sda);
 	 addr_phase(.addr(rd_addr), .rw(READ_C), .ack(read_ack));
 
 	 $timeformat(-9, 2, " ns", 20);
-	 $display("%t: I2C Master - Read Phase", $time);
+	 // $display("%t: I2C Master - Read Phase", $time);
 
 	 for(int x=0; x<num_bytes; x++) begin
 	    sda_z <= 1'b1; // TODO: HIGH Z

diff --git a/src/rtl/i2c_slave_bfm.sv b/src/rtl/i2c_slave_bfm.sv
@@ -23,8 +23,8 @@ module i2c_slave_bfm(scl, sda);
 
    task m_begin_tx;
       begin
-	 $timeformat(-9, 2, " ns", 20);
-	 $display("%t: I2C Slave - Transaction Found", $time);
+	 // $timeformat(-9, 2, " ns", 20);
+	 // $display("%t: I2C Slave - Transaction Found", $time);
 
 	 // Wait for falling edge of sda
 	 @(negedge sda_in);
@@ -42,7 +42,7 @@ module i2c_slave_bfm(scl, sda);
    task m_addr_phase;
       begin
 	 $timeformat(-9, 2, " ns", 20);
-	 $display("%t: I2C Slave - Address Phase", $time);
+	 // $display("%t: I2C Slave - Address Phase", $time);
 
 	 // Read 7-bit address
 	 for(int i=0; i<7; i++) begin
@@ -73,7 +73,7 @@ module i2c_slave_bfm(scl, sda);
    task m_write_data;
       begin
 	 $timeformat(-9, 2, " ns", 20);
-	 $display("%t: I2C Slave - Write Phase", $time);
+	 // $display("%t: I2C Slave - Write Phase", $time);
 
 	 // Read 8-bit data
 	 for(int i=0; i<8; i++) begin
@@ -109,7 +109,7 @@ module i2c_slave_bfm(scl, sda);
       begin
 	 do begin
 	    $timeformat(-9, 2, " ns", 20);
-	    $display("%t: I2C Slave - Read Phase", $time);
+	    $display("%t: I2C Slave - Read phase write data: '%h'", $time, wr_data);
 
 	    sda_z <= 1'b0;
 

diff --git a/src/tb/i2c_tb.sv b/src/tb/i2c_tb.sv
@@ -32,8 +32,9 @@ module i2c_tb;
 
       // Reads
       dut_master.m_read_data(rd_addr, rd_data, num_read_bytes, ack);
+      assert(rd_data == 8'hab);
 
-      repeat(10) #(period)
+      repeat(10) #(period);
 
       $display("============================");
       $display("======= TEST PASSED! =======");