Avoid wide signals in sensitivity lists of immediate assertions

Verilator has decent support for various types of assertions by now but dislikes wide signals (e.g., wider than 64 bits) in sensitivity lists.
michael-platzer · Sep 30, 2024 · a0525f7 · a0525f7
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commit a0525f7
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/addr_decode_dync.sv b/src/addr_decode_dync.sv
@@ -146,7 +146,7 @@ module addr_decode_dync #(
   // check_start:        Enforces a smaller start than end address.
   // check_idx:          Enforces a valid index in the rule.
   // check_overlap:      Warns if there are overlapping address regions.
-  always @(addr_map_i or config_ongoing_i) #0 begin : proc_check_addr_map
+  always @* begin : proc_check_addr_map
     if (!$isunknown(addr_map_i) && ~config_ongoing_i) begin
       for (int unsigned i = 0; i < NoRules; i++) begin
         check_start : assume (Napot || addr_map_i[i].start_addr < addr_map_i[i].end_addr ||

diff --git a/src/multiaddr_decode.sv b/src/multiaddr_decode.sv
@@ -133,7 +133,7 @@ module multiaddr_decode #(
 
   // These following assumptions check the validity of the address map.
   // check_idx: Enforces a valid index in the rule.
-  always @(addr_map_i) #0 begin : proc_check_addr_map
+  always @* begin : proc_check_addr_map
     if (!$isunknown(addr_map_i)) begin
       for (int unsigned i = 0; i < NoRules; i++) begin
         // check the SLV ids