EC413 Lab 7: Pipelined CPUs

Adding fowarding support to a standard five-stage MIPS CPU

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
CPU.v		CPU.v
README.md		README.md
RegFile.v		RegFile.v
alu.v		alu.v
alucontrol.v		alucontrol.v
discussion_tb.v		discussion_tb.v
forwarding_unit.v		forwarding_unit.v
hazardunit.v		hazardunit.v
incrementer.v		incrementer.v
jumpadd.v		jumpadd.v
load_in_counter.v		load_in_counter.v
memory2.v		memory2.v
multiplycontrol.v		multiplycontrol.v
mux2to1.v		mux2to1.v
mux2to1_1bit.v		mux2to1_1bit.v
mux2to1_5bit.v		mux2to1_5bit.v
mux3to1_32bit.v		mux3to1_32bit.v
pipecontrol.v		pipecontrol.v
reg_14bitne.v		reg_14bitne.v
reg_2bitne.v		reg_2bitne.v
reg_32bit.v		reg_32bit.v
reg_32bitne.v		reg_32bitne.v
reg_5bitne.v		reg_5bitne.v
signextend.v		signextend.v
signextend26.v		signextend26.v
stallmux.v		stallmux.v

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