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[hmac] Remove read signal and disable assert for TLUL FIFO adapter #26163

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@martin-velay martin-velay commented Feb 7, 2025

Four assertions are not covered for the HMAC:
assert_holes

That's because this FIFO is WO. The proposed solution is to remove the useless msg_fifo_rvalid signal from the RTL and to exclude the assertions.

- msg_fifo_rvalid signal is useless as it cannot be 1 as the memory is
a Write Only memory.

Signed-off-by: Martin Velay <[email protected]>
@martin-velay martin-velay self-assigned this Feb 7, 2025
@martin-velay martin-velay added IP:hmac Component:DV DV issue: testbench, test case, etc. Component:DD labels Feb 7, 2025
@martin-velay martin-velay marked this pull request as ready for review February 7, 2025 07:58
@martin-velay martin-velay requested a review from a team as a code owner February 7, 2025 07:58
@martin-velay martin-velay removed the request for review from a team February 7, 2025 10:42
- Exclude the assertions related to the read part as this particular
FIFO instance is WO, to avoid to have uncovered assertions.

Signed-off-by: Martin Velay <[email protected]>
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