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[dv] Make it an error to run an intr_test sequence when there are no interrupts #25959

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merged 2 commits into from
Jan 23, 2025

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rswarbrick
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The first commit tidies up the clkmgr hjson so that it doesn't ask us to do so (and the commit message explains what's going on). The second adds the error.

The second commit was originally part of #25864 but @alees24 (quite rightly!) thought it was worth checking it wouldn't break anything. It would have done, hence the first commit...

The block doesn't actually have any interrupts! I will follow this
change with a commit that makes it an error to run the interrupt test
sequence if there aren't any interrupts, but wanted to check this
wouldn't break any blocks.

To do so, I ran:
```
for x in $(git grep tests/intr_test '*.hjson' | cut -d : -f 1); do
  h=$(echo $x | sed 's/dv/data/' | sed 's/uvm\///' | sed 's/_sim_cfg//');
  grep interrupt_list $h >/dev/null || echo $x;
done
```

This doesn't quite work because of the parameterised versions of
`kmac`, `spi_device` and `flash_ctrl`. But a manual check of those
three blocks' hjson files shows that each has interrupts.

The only block that *does* get printed is `clkmgr`, which *doesn't*
have any interrupts! This commit removes the item from
clmkgr_sim_cfg.hjson.

Signed-off-by: Rupert Swarbrick <[email protected]>
I found this because the rom_ctrl testing was occasionally running a
very short sequence! It turns out that run_intr_test_vseq exited
quickly if there weren't actually any interrupt registers.

Rather than claiming we're doing something, let's just stop with a
failure.

Signed-off-by: Rupert Swarbrick <[email protected]>
@rswarbrick rswarbrick added the Component:DV DV issue: testbench, test case, etc. label Jan 21, 2025
@rswarbrick rswarbrick requested a review from alees24 January 21, 2025 14:22
@rswarbrick rswarbrick requested a review from a team as a code owner January 21, 2025 14:22
@rswarbrick rswarbrick requested review from marnovandermaas and removed request for a team January 21, 2025 14:22
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LGTM.

@rswarbrick rswarbrick merged commit a94d9f0 into lowRISC:master Jan 23, 2025
40 checks passed
@rswarbrick rswarbrick deleted the intr-test-tweak branch January 23, 2025 13:04
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2 participants