[test] Improve reliability of UART baud rate test #25183
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engdoreis
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Nov 22, 2024
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Hm, it failed in CI. I guess it's still flaky. |
Signed-off-by: James Wainwright <[email protected]> (commit is original to earlgrey_1.0.0) (cherry picked from commit 010023f)
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The FPGA cannot clock high enough for 1MBd or 1.5MBd, but silicon can.
This change enables a wider range of baud rates and changes how the 1MBd and 1.5MBd are restricted to be better for multitop.
Backport of #23605