[dd, prim_reg_cdc] simplifying condition to help with CCOV

prim_reg_cdc has a conditional coverage hole in the condition: `src_busy_q && src_ack` since src_ack is only 1 if `src_busy_q`. this is also ensured via the assertion `SrcAckBusyChk_A` Signed-off-by: Antonio Martinez Zambrana <[email protected]>
lowRISC · Jan 29, 2025 · f6fbdac · f6fbdac
1 parent 7780c6b
commit f6fbdac
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/hw/ip/prim/rtl/prim_reg_cdc.sv b/hw/ip/prim/rtl/prim_reg_cdc.sv
@@ -121,9 +121,9 @@ module prim_reg_cdc #(
   // be copied back.
   logic dst_to_src;
   if (DstWrReq) begin : gen_wr_req
-    assign dst_to_src = src_busy_q && src_ack || src_update && !busy;
+    assign dst_to_src = src_ack || (src_update && !busy);
   end else begin : gen_passthru
-    assign dst_to_src = src_busy_q && src_ack;
+    assign dst_to_src = src_ack;
 
     logic unused_dst_wr;
     assign unused_dst_wr = src_update ^ busy;