[prim] Rename all files to match virtual cores

We expect file names to match module names. Now that the IPs are virtual
cores, rename the files to match the module names that are the new "ABI"
(so to speak).

Adjust prim_generic, prim_xilinx, and prim_xilinx_ultrascale libraries.

Signed-off-by: Alexander Williams <[email protected]>

hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt

@@ -5,4 +5,4 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_buf.sv" -match "Parameter is not used: 'NoFpgaBuf'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_buf.sv" -match "Parameter is not used: 'NoFpgaBuf'"

hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver

@@ -2,6 +2,6 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# primitives: prim_generic_clock_buf
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_buf.sv} -regexp {Parameter '(NoFpgaBuf|RegionSel)' not used} \
+# primitives: prim_clock_buf
+waive -rules PARAM_NOT_USED -location {prim_clock_buf.sv} -regexp {Parameter '(NoFpgaBuf|RegionSel)' not used} \
       -comment "parameter unused but required to maintain uniform interface"

hw/ip/prim_generic/lint/prim_generic_clock_div.waiver

@@ -2,19 +2,19 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_clock_div
+# waiver file for prim_clock_div
 
-waive -rules CLOCK_EDGE -location {prim_generic_clock_div.sv} -msg {Falling edge of clock 'clk_i' used here, should use rising edge} \
+waive -rules CLOCK_EDGE -location {prim_clock_div.sv} -msg {Falling edge of clock 'clk_i' used here, should use rising edge} \
       -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
 
-waive -rules DUAL_EDGE_CLOCK -location {prim_generic_clock_div.sv} -regexp {.*} \
+waive -rules DUAL_EDGE_CLOCK -location {prim_clock_div.sv} -regexp {.*} \
       -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
 
-waive -rules CLOCK_MUX -location {prim_generic_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \
+waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \
       -comment "A mux is used during scan bypass, and for switching between div by 2 and div by 1 clocks"
 
-waive -rules CLOCK_USE -location {prim_generic_clock_div.sv} -regexp {'clk_i' is connected to 'prim_clock_mux2' port 'clk1_i', and used as a clock} \
+waive -rules CLOCK_USE -location {prim_clock_div.sv} -regexp {'clk_i' is connected to 'prim_clock_mux2' port 'clk1_i', and used as a clock} \
       -comment "This clock mux usage is OK."
 
-waive -rules SAME_NAME_TYPE -location {prim_generic_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \
+waive -rules SAME_NAME_TYPE -location {prim_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \
       -comment "Reused parameter name."

hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt

@@ -5,5 +5,5 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_gating.sv" -match "Parameter is not used: 'NoFpgaGate'"
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_gating.sv" -match "Parameter is not used: 'FpgaBufGlobal'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_gating.sv" -match "Parameter is not used: 'NoFpgaGate'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_gating.sv" -match "Parameter is not used: 'FpgaBufGlobal'"

hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver

@@ -3,11 +3,11 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # primitives: prim_clock_gating
-waive -rules LATCH                -location {prim_generic_clock_gating.sv} -regexp {'en_latch' is a latch} \
+waive -rules LATCH                -location {prim_clock_gating.sv} -regexp {'en_latch' is a latch} \
       -comment "clock gating cell creates a latch"
-waive -rules COMBO_NBA            -location {prim_generic_clock_gating.sv} -regexp {Non-blocking assignment to 'en_latch'} \
+waive -rules COMBO_NBA            -location {prim_clock_gating.sv} -regexp {Non-blocking assignment to 'en_latch'} \
       -comment "clock gating cell creates a latch"
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_gating.sv} -regexp {Parameter 'NoFpgaGate' not used} \
+waive -rules PARAM_NOT_USED -location {prim_clock_gating.sv} -regexp {Parameter 'NoFpgaGate' not used} \
       -comment "parameter unused but required to maintain uniform interface"
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_gating.sv} -regexp {Parameter 'FpgaBufGlobal' not used} \
+waive -rules PARAM_NOT_USED -location {prim_clock_gating.sv} -regexp {Parameter 'FpgaBufGlobal' not used} \
       -comment "parameter unused but required to maintain uniform interface"

hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt

@@ -5,4 +5,4 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_mux2.sv" -match "Parameter is not used: 'NoFpgaBufG'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_mux2.sv" -match "Parameter is not used: 'NoFpgaBufG'"

hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver

@@ -4,5 +4,5 @@
 #
 # waiver file for prim_clock_mux2
 
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_mux2.sv} -regexp {.*Parameter 'NoFpgaBufG' not used in.*} \
+waive -rules PARAM_NOT_USED -location {prim_clock_mux2.sv} -regexp {.*Parameter 'NoFpgaBufG' not used in.*} \
       -comment "This parameter serves no function in the generic model"

hw/ip/prim_generic/lint/prim_generic_flash.waiver

@@ -2,8 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_flash
+# waiver file for prim_flash
 
 # The prim generic module does not make use of the IO ports
-waive -rules INOUT_AS_IN -location {prim_generic_flash.sv} \
+waive -rules INOUT_AS_IN -location {prim_flash.sv} \
       -regexp {Inout port 'flash_.*_io' has no driver}

hw/ip/prim_generic/lint/prim_generic_otp.vlt

@@ -6,5 +6,5 @@
 `verilator_config
 
 // The generic OTP module doesn't use vendor-specific parameters
-lint_off -rule UNUSED -file "*/rtl/prim_generic_otp.sv" -match "*VendorTestOffset*"
-lint_off -rule UNUSED -file "*/rtl/prim_generic_otp.sv" -match "*VendorTestSize*"
+lint_off -rule UNUSED -file "*/rtl/prim_otp.sv" -match "*VendorTestOffset*"
+lint_off -rule UNUSED -file "*/rtl/prim_otp.sv" -match "*VendorTestSize*"

hw/ip/prim_generic/lint/prim_generic_otp.waiver

@@ -7,10 +7,10 @@ waive -rules {CONST_FF} -location {prim_ram_1p_adv.sv} \
       -msg {Flip-flop 'rerror_q' is driven by constant zeros in module 'prim_ram_1p_adv' (Depth=1024,Width=22,EnableInputPipeline=1,EnableOutputPipeline=1)} \
       -comment "The read error bits are unused and hence set to zero."
 
-waive -rules {INOUT_AS_IN} -location {prim_generic_otp.sv} \
-      -msg {Inout port 'ext_voltage_io' has no driver in module 'prim_generic_otp'} \
+waive -rules {INOUT_AS_IN} -location {prim_otp.sv} \
+      -msg {Inout port 'ext_voltage_io' has no driver in module 'prim_otp'} \
       -comment "This signal is not driven in the generic model."
 
-waive -rules {PARAM_NOT_USED} -location {prim_generic_otp.sv} \
-      -regexp {Parameter '(VendorTestOffset|VendorTestSize)' not used in module 'prim_generic_otp'} \
+waive -rules {PARAM_NOT_USED} -location {prim_otp.sv} \
+      -regexp {Parameter '(VendorTestOffset|VendorTestSize)' not used in module 'prim_otp'} \
       -comment "These two parameters are not used in the generic model."

hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver

@@ -2,26 +2,26 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_pad_wrapper
+# waiver file for prim_pad_wrapper
 # note that this code is NOT synthesizable and meant for sim only
 
-waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} -location {prim_generic_pad_wrapper.sv} \
+waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} -location {prim_pad_wrapper.sv} \
       -comment "This is a bidirectional pad inout."
 waive -rules TRI_DRIVER -regexp {'in_raw_o' is driven by a tristate driver} \
       -comment "This is a bidirectional pad inout."
-waive -rules MULTI_DRIVEN -regexp {.* drivers on 'inout_io' here} -location {prim_generic_pad_wrapper.sv} \
+waive -rules MULTI_DRIVEN -regexp {.* drivers on 'inout_io' here} -location {prim_pad_wrapper.sv} \
       -comment "The pad simulation model has multiple drivers to emulate different IO terminations."
-waive -rules SELF_ASSIGN -regexp {LHS signal 'inout_io' encountered on the RHS of a continuous assignment statement} -location {prim_generic_pad_wrapper.sv} \
+waive -rules SELF_ASSIGN -regexp {LHS signal 'inout_io' encountered on the RHS of a continuous assignment statement} -location {prim_pad_wrapper.sv} \
       -comment "This implements a keeper termination (it's basically an explicit TRIREG)"
-waive -rules DRIVE_STRENGTH -regexp {Drive strength .* encountered on assignment to 'inout_io'} -location {prim_generic_pad_wrapper.sv} \
+waive -rules DRIVE_STRENGTH -regexp {Drive strength .* encountered on assignment to 'inout_io'} -location {prim_pad_wrapper.sv} \
       -comment "The pad simulation model uses driving strength attributes to emulate different IO terminations."
-waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i*' is not read from} -location {prim_generic_pad_wrapper.sv} \
+waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i*' is not read from} -location {prim_pad_wrapper.sv} \
       -comment "Some IO attributes may not be implemented."
-waive -rules Z_USE -regexp {Constant with 'Z literal value '1'bz' encountered} -location {prim_generic_pad_wrapper.sv} \
+waive -rules Z_USE -regexp {Constant with 'Z literal value '1'bz' encountered} -location {prim_pad_wrapper.sv} \
       -comment "This z assignment is correct."
-waive -rules PARAM_NOT_USED -regexp {Parameter 'Variant' not used in module 'prim_generic_pad_wrapper'} -location {prim_generic_pad_wrapper.sv} \
+waive -rules PARAM_NOT_USED -regexp {Parameter 'Variant' not used in module 'prim_pad_wrapper'} -location {prim_pad_wrapper.sv} \
       -comment "This parameter has been provisioned for later and is currently unused."
-waive -rules PARAM_NOT_USED -regexp {Parameter 'ScanRole' not used in module 'prim_generic_pad_wrapper'} -location {prim_generic_pad_wrapper.sv} \
+waive -rules PARAM_NOT_USED -regexp {Parameter 'ScanRole' not used in module 'prim_pad_wrapper'} -location {prim_pad_wrapper.sv} \
       -comment "This parameter has been provisioned for later and is currently unused."
-waive -rules INPUT_NOT_READ -msg {Input port 'clk_scan_i' is not read from in module 'prim_generic_pad_wrapper'} \
+waive -rules INPUT_NOT_READ -msg {Input port 'clk_scan_i' is not read from in module 'prim_pad_wrapper'} \
       -comment "This clock is not read in RTL since it will be connected after synthesis during DFT insertion"

hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver

@@ -2,11 +2,11 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_1p
+# waiver file for prim_ram_1p
 
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1p.sv.* is not read from in module 'prim_generic_ram_1p'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_1p.sv.* is not read from in module 'prim_ram_1p'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
-waive -rules IFDEF_CODE -location {prim_generic_ram_1p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+waive -rules IFDEF_CODE -location {prim_ram_1p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"

hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver

@@ -2,11 +2,11 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_1r1w
+# waiver file for prim_ram_1r1w
 
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1r1w.sv.* is not read from in module 'prim_generic_ram_1r1w'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_1r1w.sv.* is not read from in module 'prim_ram_1r1w'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
-waive -rules IFDEF_CODE -location {prim_generic_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+waive -rules IFDEF_CODE -location {prim_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"

hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt

@@ -6,4 +6,4 @@
 `verilator_config
 
 // That is the nature of a dual-port memory: both write ports can access the same storage simultaneously.
-lint_off -rule MULTIDRIVEN -file "*/rtl/prim_generic_ram_2p.sv" -match "Signal has multiple driving blocks with different clocking: '*.mem'*"
+lint_off -rule MULTIDRIVEN -file "*/rtl/prim_ram_2p.sv" -match "Signal has multiple driving blocks with different clocking: '*.mem'*"

hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver

@@ -2,13 +2,13 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_2p
+# waiver file for prim_ram_2p
 
-waive -rules MULTI_PROC_ASSIGN -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \
+waive -rules MULTI_PROC_ASSIGN -location {prim_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \
       -comment "That is the nature of a dual-port memory: both write ports can access the same storage simultaneously"
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_2p.sv.* is not read from in module 'prim_generic_ram_2p'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_2p.sv.* is not read from in module 'prim_ram_2p'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
-waive -rules IFDEF_CODE -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+waive -rules IFDEF_CODE -location {prim_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"

hw/ip/prim_generic/lint/prim_generic_rom.waiver

@@ -2,7 +2,7 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_rom
+# waiver file for prim_rom
 
-waive -rules NOT_DRIVEN  -location {prim_generic_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_generic_rom'} \
+waive -rules NOT_DRIVEN  -location {prim_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_rom'} \
       -comment "since this is a ROM, the signal mem has no driver, but it is populated using an initialization file"

hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver

@@ -2,12 +2,12 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_usb_diff_rx
+# waiver file for prim_usb_diff_rx
 # note that this code is NOT synthesizable and meant for sim only
 
-waive -rules TRI_DRIVER -regexp {'(input_pi|input_ni)' is driven by a tristate driver} -location {prim_generic_usb_diff_rx.sv} \
+waive -rules TRI_DRIVER -regexp {'(input_pi|input_ni)' is driven by a tristate driver} -location {prim_usb_diff_rx.sv} \
       -comment "This models the pullup behavior, hence the TRI driver."
-waive -rules MULTI_DRIVEN -regexp {'(input_pi|input_ni)' has 2 drivers, also driven at} -location {prim_generic_usb_diff_rx.sv} \
+waive -rules MULTI_DRIVEN -regexp {'(input_pi|input_ni)' has 2 drivers, also driven at} -location {prim_usb_diff_rx.sv} \
       -comment "The simulation model has multiple drivers to emulate different IO terminations."
-waive -rules DRIVE_STRENGTH -regexp {Drive strength '\(weak0,pull1\)' encountered on assignment to '(input_pi|input_ni)'} -location {prim_generic_usb_diff_rx.sv} \
+waive -rules DRIVE_STRENGTH -regexp {Drive strength '\(weak0,pull1\)' encountered on assignment to '(input_pi|input_ni)'} -location {prim_usb_diff_rx.sv} \
       -comment "The simulation model uses driving strength attributes to emulate different IO terminations."

hw/ip/prim_generic/prim_generic_and2.core

@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_and2.sv
+      - rtl/prim_and2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_buf.core

@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_buf.sv
+      - rtl/prim_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_clock_buf.core

@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_clock_buf.sv
+      - rtl/prim_clock_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_clock_div.core

@@ -16,7 +16,7 @@ filesets:
       - lowrisc:prim:clock_inv
       - lowrisc:prim:clock_buf
     files:
-      - rtl/prim_generic_clock_div.sv
+      - rtl/prim_clock_div.sv
     file_type: systemVerilogSource
 
   files_ascentlint_waiver:

hw/ip/prim_generic/prim_generic_clock_gating.core

@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_clock_gating.sv
+      - rtl/prim_clock_gating.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_clock_inv.core

@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:clock_mux2
     files:
-      - rtl/prim_generic_clock_inv.sv
+      - rtl/prim_clock_inv.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_clock_mux2.core

@@ -13,7 +13,7 @@ filesets:
     depend:
       - lowrisc:prim:assert
     files:
-      - rtl/prim_generic_clock_mux2.sv
+      - rtl/prim_clock_mux2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_flash.core

@@ -19,7 +19,7 @@ filesets:
       - lowrisc:ip:flash_ctrl_prim_reg_top
     files:
       - rtl/prim_generic_flash_bank.sv
-      - rtl/prim_generic_flash.sv
+      - rtl/prim_flash.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_flop.core

@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_flop.sv
+      - rtl/prim_flop.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_flop_2sync.core

@@ -16,7 +16,7 @@ filesets:
       # Needed for DV.
       - lowrisc:prim:cdc_rand_delay
     files:
-      - rtl/prim_generic_flop_2sync.sv
+      - rtl/prim_flop_2sync.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_flop_en.core

@@ -13,7 +13,7 @@ filesets:
     depend:
       - lowrisc:prim:sec_anchor
     files:
-      - rtl/prim_generic_flop_en.sv
+      - rtl/prim_flop_en.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_otp.core

@@ -19,7 +19,7 @@ filesets:
       - lowrisc:prim:otp_pkg
       - lowrisc:ip:otp_ctrl_prim_reg_top
     files:
-      - rtl/prim_generic_otp.sv
+      - rtl/prim_otp.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_pad_attr.core

@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_generic_pad_attr.sv
+      - rtl/prim_pad_attr.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_pad_wrapper.core

@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_generic_pad_wrapper.sv
+      - rtl/prim_pad_wrapper.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:

hw/ip/prim_generic/prim_generic_ram_1p.core

@@ -15,7 +15,7 @@ filesets:
       - lowrisc:prim:ram_1p_pkg
       - lowrisc:prim:util_memload
     files:
-      - rtl/prim_generic_ram_1p.sv
+      - rtl/prim_ram_1p.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver: