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Update lowrisc_ibex to lowRISC/ibex@54985d21
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Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
54985d21b055967c39d0a77b45ae0d573b55b0f7

* [rtl] Fix counter reset value on FPGA (Pascal Nasahl)
* [ci] remove Azure Pipelines (Gary Guo)

Signed-off-by: Pascal Nasahl <[email protected]>
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nasahlpa committed Nov 29, 2024
1 parent f4ecac6 commit 1de26c4
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Showing 3 changed files with 14 additions and 11 deletions.
2 changes: 1 addition & 1 deletion hw/vendor/lowrisc_ibex.lock.hjson
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Expand Up @@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/ibex.git
rev: 84232a5bfa8b020cd05718b2ae21d8584c942df8
rev: 54985d21b055967c39d0a77b45ae0d573b55b0f7
}
}
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Expand Up @@ -84,7 +84,7 @@ V2 Checklist
+---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Tests | SIM_FW_SIMULATED | N/A | No ROM or firmware present. |
+---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Regression | SIM_NIGHTLY_REGRESSION_V2 | Complete | Regression run in Azure pipeline only accessible to OpenTitan members. |
| Regression | SIM_NIGHTLY_REGRESSION_V2 | Complete | Regression run in GitHub Actions only accessible to OpenTitan members. |
| | | | Publicly viewable reports on the `OpenTitan regression dashboard <https://reports.opentitan.org/hw/top_earlgrey/dv/summary/latest/report.html>`_ are planned for V3. |
+---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Coverage | SIM_CODE_COVERAGE_V2 | Complete | Coverage results available in nightly regression run. |
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21 changes: 12 additions & 9 deletions hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv
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Expand Up @@ -51,12 +51,17 @@ module ibex_counter #(
end

`ifdef FPGA_XILINX
// Set DSP pragma for supported xilinx FPGAs
localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
(* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;

// DSP output register requires synchronous reset.
`define COUNTER_FLOP_RST posedge clk_i
// On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
// counter.
if (CounterWidth < 49) begin : g_dsp_counter
// Set DSP pragma for supported xilinx FPGAs
(* use_dsp = "yes" *) logic [CounterWidth-1:0] counter_q;
// DSP output register requires synchronous reset.
`define COUNTER_FLOP_RST posedge clk_i
end else begin : g_no_dsp_counter
(* use_dsp = "no" *) logic [CounterWidth-1:0] counter_q;
`define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
end
`else
logic [CounterWidth-1:0] counter_q;

Expand All @@ -65,6 +70,7 @@ module ibex_counter #(

// Counter flop
always_ff @(`COUNTER_FLOP_RST) begin
`undef COUNTER_FLOP_RST
if (!rst_ni) begin
counter_q <= '0;
end else begin
Expand Down Expand Up @@ -98,6 +104,3 @@ module ibex_counter #(
assign counter_val_o = counter;

endmodule

// Keep helper defines file-local.
`undef COUNTER_FLOP_RST

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