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[opentitantool] Rescue erases other slot by default #4220

[opentitantool] Rescue erases other slot by default

[opentitantool] Rescue erases other slot by default #4220

Triggered via pull request January 9, 2025 18:49
Status Success
Total duration 3h 4m 10s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 58s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1m 48s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
1m 56s
Earl Grey for CW310 / Build bitstream
Lint (slow)
11m 20s
Lint (slow)
Build documentation
5m 15s
Build documentation
Airgapped build
9m 59s
Airgapped build
Verible lint
1m 7s
Verible lint
Run OTBN smoke Test
2m 44s
Run OTBN smoke Test
Run OTBN crypto tests
21m 26s
Run OTBN crypto tests
Verilated English Breakfast
8m 40s
Verilated English Breakfast
Verilated Earl Grey
1h 16m
Verilated Earl Grey
CW305's Bitstream
22m 18s
CW305's Bitstream
Build Docker Containers
3m 2s
Build Docker Containers
Build and test software
14m 29s
Build and test software
CW310 ROM_EXT Tests  /  FPGA test
8m 13s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
25m 15s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
36m 25s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
35m 35s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 19s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
46s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
6m 27s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
18m 4s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 32s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
44m 56s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
4m 11s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
42m 29s
CW310 ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
19s
Verify FPGA jobs
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Annotations

8 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.4 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
56.1 KB
execute_rom_ext_fpga_tests_cw310-targets
519 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
13.2 KB
execute_rom_ext_fpga_tests_cw340-targets
437 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.22 KB
execute_rom_fpga_tests_cw310-targets
1.76 KB
execute_rom_fpga_tests_cw310-test-results
47.4 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
36.9 KB
execute_sival_fpga_tests_cw340-targets
502 Bytes
execute_sival_fpga_tests_cw340-test-results
40.1 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.25 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
185 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
435 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
17 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.26 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
44.4 KB
partial-build-bin-chip_earlgrey_cw310
6.04 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.02 MB
partial-build-bin-chip_earlgrey_cw340
9.9 MB
sw_build_test-test-results
75.1 KB
verilated_englishbreakfast
6.99 MB
verilator_earlgrey-test-results
8.89 KB