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[bazel] Define rules-based CC lowRISC toolchain #4208

[bazel] Define rules-based CC lowRISC toolchain

[bazel] Define rules-based CC lowRISC toolchain #4208

Triggered via pull request January 9, 2025 16:07
Status Success
Total duration 3h 53m 28s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 6m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 42m
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
1h 7m
Earl Grey for CW310 / Build bitstream
Lint (slow)
12m 8s
Lint (slow)
Build documentation
5m 9s
Build documentation
Airgapped build
9m 57s
Airgapped build
Verible lint
1m 11s
Verible lint
Run OTBN smoke Test
2m 46s
Run OTBN smoke Test
Run OTBN crypto tests
24m 16s
Run OTBN crypto tests
Verilated English Breakfast
8m 45s
Verilated English Breakfast
Verilated Earl Grey
1h 20m
Verilated Earl Grey
CW305's Bitstream
26m 25s
CW305's Bitstream
Build Docker Containers
2m 39s
Build Docker Containers
Build and test software
19m 42s
Build and test software
CW310 ROM_EXT Tests  /  FPGA test
8m 2s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
24m 43s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
41m 58s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
33m 18s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 43s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
49s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
6m 35s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
18m 14s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 10s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
42m 56s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
3m 39s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
43m 25s
CW310 ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
19s
Verify FPGA jobs
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Annotations

8 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.4 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59.7 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
55.6 KB
execute_rom_ext_fpga_tests_cw310-targets
519 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
13 KB
execute_rom_ext_fpga_tests_cw340-targets
437 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.12 KB
execute_rom_fpga_tests_cw310-targets
1.76 KB
execute_rom_fpga_tests_cw310-test-results
47.5 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
37.2 KB
execute_sival_fpga_tests_cw340-targets
502 Bytes
execute_sival_fpga_tests_cw340-test-results
39.6 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.25 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
187 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
435 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
17.3 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.25 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.4 KB
partial-build-bin-chip_earlgrey_cw310
6.04 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.02 MB
partial-build-bin-chip_earlgrey_cw340
9.9 MB
sw_build_test-test-results
75.1 KB
verilated_englishbreakfast
6.99 MB
verilator_earlgrey-test-results
8.96 KB