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[bazel] Define rules-based CC lowRISC toolchain #4193

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[bazel] Define rules-based CC lowRISC toolchain

[bazel] Define rules-based CC lowRISC toolchain #4193

Triggered via pull request January 9, 2025 14:10
@jwnrtjwnrt
synchronize #25810
jwnrt:rules-cc-lowrisc-toolchain
Status Failure
Total duration 15m 49s
Artifacts 3

ci.yml

on: pull_request
Lint (quick)
3m 5s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
2m 14s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
2m 19s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
2m 16s
Earl Grey for CW310 / Build bitstream
Lint (slow)
12m 5s
Lint (slow)
Build documentation
5m 33s
Build documentation
Airgapped build
5m 46s
Airgapped build
Verible lint
1m 8s
Verible lint
Run OTBN smoke Test
2m 34s
Run OTBN smoke Test
Run OTBN crypto tests
1m 35s
Run OTBN crypto tests
Verilated English Breakfast
7m 15s
Verilated English Breakfast
Verilated Earl Grey
2m 55s
Verilated Earl Grey
CW305's Bitstream
1m 35s
CW305's Bitstream
Build Docker Containers
2m 32s
Build Docker Containers
Build and test software
2m 33s
Build and test software
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
20s
Verify FPGA jobs
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Annotations

18 errors and 3 warnings
Run OTBN crypto tests
Process completed with exit code 1.
CW305's Bitstream
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Verilated Earl Grey
Process completed with exit code 1.
Airgapped build
Process completed with exit code 2.
Verilated English Breakfast
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
Process completed with exit code 1.
Earl Grey for CW310 Hyperdebug / Build bitstream
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.
Earl Grey for CW310 Hyperdebug / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.
Earl Grey for CW340 / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
sw_build_test-test-results
201 Bytes
verilated_englishbreakfast
6.99 MB
verilator_earlgrey-test-results
201 Bytes