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[dv,pwm] Synchronize to monitor pulses when blink state changes #4150

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[dv,pwm] Synchronize to monitor pulses when blink state changes

[dv,pwm] Synchronize to monitor pulses when blink state changes #4150

Triggered via pull request January 8, 2025 17:34
@alees24alees24
opened #25815
alees24:pwm-settle
Status Failure
Total duration 4h 53m 25s
Artifacts 31

ci.yml

on: pull_request
Lint (quick)
3m 8s
Lint (quick)
Earl Grey for CW310  /  Build bitstream
1m 52s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
1m 52s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 52s
Earl Grey for CW310 Hyperdebug / Build bitstream
Lint (slow)
11m 58s
Lint (slow)
Build documentation
5m 1s
Build documentation
Airgapped build
8m 54s
Airgapped build
Verible lint
1m 4s
Verible lint
Run OTBN smoke Test
2m 32s
Run OTBN smoke Test
Run OTBN crypto tests
20m 49s
Run OTBN crypto tests
Verilated English Breakfast
8m 57s
Verilated English Breakfast
Verilated Earl Grey
1h 24m
Verilated Earl Grey
CW305's Bitstream
23m 11s
CW305's Bitstream
Build Docker Containers
2m 58s
Build Docker Containers
Build and test software
13m 49s
Build and test software
CW310 Test ROM Tests  /  FPGA test
3m 37s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
41m 57s
CW310 ROM Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 24s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
51s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
7m 12s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
18m 46s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 4s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
45m 40s
CW340 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
7m 46s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
25m 52s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
41m 49s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
35m 21s
CW310 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
20s
Verify FPGA jobs
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Annotations

9 errors and 2 warnings
Verible lint
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
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Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Verible lint: hw/ip/pwm/dv/env/pwm_scoreboard.sv#L293
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default] Raw Output: message:"Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/ip/pwm/dv/env/pwm_scoreboard.sv" range:{start:{line:293 column:7}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Verible lint: hw/ip/pwm/dv/env/pwm_scoreboard.sv#L414
[verible-verilog-lint] reported by reviewdog 🐶 Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default] Raw Output: message:"Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/ip/pwm/dv/env/pwm_scoreboard.sv" range:{start:{line:414 column:5}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.4 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
59.9 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
56.3 KB
execute_rom_ext_fpga_tests_cw310-targets
519 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
12.9 KB
execute_rom_ext_fpga_tests_cw340-targets
437 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.24 KB
execute_rom_fpga_tests_cw310-targets
1.76 KB
execute_rom_fpga_tests_cw310-test-results
47.5 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
37 KB
execute_sival_fpga_tests_cw340-targets
502 Bytes
execute_sival_fpga_tests_cw340-test-results
39.8 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.25 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
188 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
435 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
18.4 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.28 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.1 KB
partial-build-bin-chip_earlgrey_cw310
6.04 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.02 MB
partial-build-bin-chip_earlgrey_cw340
9.9 MB
sw_build_test-test-results
75.1 KB
verilated_englishbreakfast
6.99 MB
verilator_earlgrey-test-results
8.87 KB