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[bazel] Define rules-based CC lowRISC toolchain #4147

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[bazel] Define rules-based CC lowRISC toolchain

[bazel] Define rules-based CC lowRISC toolchain #4147

Re-run triggered January 9, 2025 08:08
@jwnrtjwnrt
#25810
jwnrt:rules-cc-lowrisc-toolchain
Status Failure
Total duration 1h 8m 8s
Artifacts 32

ci.yml

on: pull_request
Lint (quick)
3m 30s
Lint (quick)
Earl Grey for CW310  /  Build bitstream
1h 5m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 11m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 35m
Earl Grey for CW340 / Build bitstream
Lint (slow)
11m 58s
Lint (slow)
Build documentation
4m 55s
Build documentation
Airgapped build
10m 42s
Airgapped build
Verible lint
1m 9s
Verible lint
Run OTBN smoke Test
2m 28s
Run OTBN smoke Test
Run OTBN crypto tests
25m 41s
Run OTBN crypto tests
Verilated English Breakfast
1h 7m
Verilated English Breakfast
Verilated Earl Grey
1h 18m
Verilated Earl Grey
CW305's Bitstream
23m 21s
CW305's Bitstream
Build Docker Containers
3m 17s
Build Docker Containers
Build and test software
18m 43s
Build and test software
CW310 Test ROM Tests  /  FPGA test
3m 24s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
46m 54s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
7m 57s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
28m 46s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
2m 29s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
34m 5s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 22s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
45s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
5m 29s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
17m 6s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 46s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
42m 19s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
18s
Verify FPGA jobs
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Annotations

10 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
CW310 SiVal ROM_EXT Tests / FPGA test
Process completed with exit code 1.
Verilated English Breakfast
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.4 MB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.25 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
201 Bytes
verilated_englishbreakfast
6.99 MB