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Cherry-pick to earlgrey_1.0.0: [sival] Enable CW310 exec env on rv_dm tests #2363

Cherry-pick to earlgrey_1.0.0: [sival] Enable CW310 exec env on rv_dm tests

Cherry-pick to earlgrey_1.0.0: [sival] Enable CW310 exec env on rv_dm tests #2363

Re-run triggered November 26, 2024 09:28
Status Success
Total duration 47m 15s
Artifacts 34

ci.yml

on: pull_request
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 56s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
1m 55s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
1m 56s
Earl Grey for CW340 / Build bitstream
Lint (slow)
14m 14s
Lint (slow)
Airgapped build
13m 41s
Airgapped build
Verible lint
1m 1s
Verible lint
Verilated English Breakfast
7m 49s
Verilated English Breakfast
Verilated Earl Grey
1h 5m
Verilated Earl Grey
CW305's Bitstream
24m 23s
CW305's Bitstream
Build Docker Containers
2m 55s
Build Docker Containers
Build and test software
12m 8s
Build and test software
CW310 SiVal Tests  /  FPGA test
33m 26s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
23m 39s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
32m 44s
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
13m 29s
CW310 ROM_EXT Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
5m 25s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
27m 32s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
4m 30s
CW310 ROM_EXT Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
1m 43s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
1m 29s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
1m 36s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
4m 37s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
2m 12s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
8m 26s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
21s
Verify FPGA jobs
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Annotations

2 errors
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 127.

Artifacts

Produced during runtime
Name Size
execute_sival_rom_ext_fpga_tests_cw310-targets
1.8 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
159 KB