Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

afc_timing: add upstream debug registers. #59

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

afc_timing: add upstream debug registers. #59

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 20 additions & 0 deletions modules/afc_timing.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ struct afc_timing {
struct {
uint32_t config, pulses, count, evt, dly, wdt;
} trigger[NUM_CHANNELS];
uint32_t dbg_ctl, dbg_cfg_1, dbg_cfg_2, dbg_sta;
};

Core::Core(struct pcie_bars &bars):
Expand Down Expand Up @@ -95,6 +96,13 @@ Core::Core(struct pcie_bars &bars):
PRINTER("CH_EVT", "Channel event code", PrinterType::value),
PRINTER("CH_DLY", "Channel delay to trigger output", PrinterType::value),
PRINTER("CH_WDT", "Channel trigger output width", PrinterType::value),

PRINTER("DBG_EN", "Enables upstream debug mode", PrinterType::enable),
PRINTER("DBG_EVT_DS_START", "Downstream start event", PrinterType::value),
PRINTER("DBG_EVT_US", "Upstream event", PrinterType::value),
PRINTER("DBG_EVT_SPACING", "Upstream event spacing", PrinterType::value),
PRINTER("DBG_EVT_REPS", "Upstream event repetitions", PrinterType::value),
PRINTER("DBG_COUNTER", "Counts how many times the debugging procedure was triggered", PrinterType::value),
}),
CONSTRUCTOR_REGS(struct afc_timing)
{
Expand Down Expand Up @@ -163,6 +171,17 @@ void Core::decode()
add_channel("CH_DLY", i, rf_whole_register(trigger.dly));
add_channel("CH_WDT", i, rf_whole_register(trigger.wdt));
}

pt = &regs.dbg_ctl;
add_general("DBG_EN", rf_get_bit(*pt, TIMING_DBG_CTL_EN));
add_general("DBG_COUNTER_RST", rf_get_bit(*pt, TIMING_DBG_CTL_COUNTER_RST));
pt = &regs.dbg_cfg_1;
add_general("DBG_EVT_DS_START", rf_extract_value(*pt, TIMING_DBG_CFG_1_EVT_DS_START_MASK));
add_general("DBG_EVT_US", rf_extract_value(*pt, TIMING_DBG_CFG_1_EVT_US_MASK));
add_general("DBG_EVT_SPACING", rf_extract_value(*pt, TIMING_DBG_CFG_1_EVT_SPACING_MASK));

add_general("DBG_EVT_REPS", rf_whole_register(regs.dbg_cfg_2));
add_general("DBG_COUNTER", regs.dbg_sta);
}

Controller::Controller(struct pcie_bars &bars):
Expand Down Expand Up @@ -226,6 +245,7 @@ void Controller::unset_commands()
write_general("RST_LOCKED_LTCS", 0);
for (unsigned i = 0; i < NUM_CHANNELS; i++)
write_channel("CH_COUNT_RST", i, 0);
write_general("DBG_COUNTER_RST", 0);
}

} /* namespace afc_timing */
54 changes: 53 additions & 1 deletion modules/hw/wb_slave_afc_timing_regs.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

* File : wb_slave_afc_timing_regs.h
* Author : auto-generated by wbgen2 from wb_slave_afc_timing_sirius.wb
* Created : Mon Oct 7 16:07:57 2024
* Created : Fri Nov 8 15:29:01 2024
* Standard : ANSI C

THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_afc_timing_sirius.wb
Expand Down Expand Up @@ -848,6 +848,50 @@
/* definitions for register: FMC2 delay 4 */

/* definitions for register: FMC2 width 4 */

/* definitions for register: Upstream debug: control */

/* definitions for field: Enable in reg: Upstream debug: control */
#define TIMING_DBG_CTL_EN WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Counter reset in reg: Upstream debug: control */
#define TIMING_DBG_CTL_COUNTER_RST WBGEN2_GEN_MASK(1, 1)

/* definitions for register: Upstream debug: configurations 1 */

/* definitions for field: Downstream start event in reg: Upstream debug: configurations 1 */
#define TIMING_DBG_CFG_1_EVT_DS_START_MASK WBGEN2_GEN_MASK(0, 8)
#define TIMING_DBG_CFG_1_EVT_DS_START_SHIFT 0
#define TIMING_DBG_CFG_1_EVT_DS_START_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define TIMING_DBG_CFG_1_EVT_DS_START_R(reg) WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for field: Upstream event in reg: Upstream debug: configurations 1 */
#define TIMING_DBG_CFG_1_EVT_US_MASK WBGEN2_GEN_MASK(8, 8)
#define TIMING_DBG_CFG_1_EVT_US_SHIFT 8
#define TIMING_DBG_CFG_1_EVT_US_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define TIMING_DBG_CFG_1_EVT_US_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Upstream debug: event spacing in reg: Upstream debug: configurations 1 */
#define TIMING_DBG_CFG_1_EVT_SPACING_MASK WBGEN2_GEN_MASK(16, 8)
#define TIMING_DBG_CFG_1_EVT_SPACING_SHIFT 16
#define TIMING_DBG_CFG_1_EVT_SPACING_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define TIMING_DBG_CFG_1_EVT_SPACING_R(reg) WBGEN2_GEN_READ(reg, 16, 8)

/* definitions for register: Upstream debug: configurations 2 */

/* definitions for field: Upstream event repetitions in reg: Upstream debug: configurations 2 */
#define TIMING_DBG_CFG_2_EVT_REPS_MASK WBGEN2_GEN_MASK(0, 32)
#define TIMING_DBG_CFG_2_EVT_REPS_SHIFT 0
#define TIMING_DBG_CFG_2_EVT_REPS_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TIMING_DBG_CFG_2_EVT_REPS_R(reg) WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Upstream debug: status */

/* definitions for field: Counter in reg: Upstream debug: status */
#define TIMING_DBG_STA_COUNTER_MASK WBGEN2_GEN_MASK(0, 32)
#define TIMING_DBG_STA_COUNTER_SHIFT 0
#define TIMING_DBG_STA_COUNTER_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TIMING_DBG_STA_COUNTER_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG Status */
#define TIMING_REG_STAT 0x00000000
/* [0x4]: REG alive */
Expand Down Expand Up @@ -1092,4 +1136,12 @@
#define TIMING_REG_FMC2CH4_DLY 0x000001e0
/* [0x1e4]: REG FMC2 width 4 */
#define TIMING_REG_FMC2CH4_WDT 0x000001e4
/* [0x1e8]: REG Upstream debug: control */
#define TIMING_REG_DBG_CTL 0x000001e8
/* [0x1ec]: REG Upstream debug: configurations 1 */
#define TIMING_REG_DBG_CFG_1 0x000001ec
/* [0x1f0]: REG Upstream debug: configurations 2 */
#define TIMING_REG_DBG_CFG_2 0x000001f0
/* [0x1f4]: REG Upstream debug: status */
#define TIMING_REG_DBG_STA 0x000001f4
#endif
Loading