Completed refactoring

examples/segment20176/segment20176.asm

@@ -0,0 +1,21 @@
+@1
+MOV UP, ACC
+SUB RIGHT
+MOV ACC, DOWN
+
+@2
+MOV UP, LEFT
+
+@5
+MOV UP, ACC
+MOV ACC, DOWN
+MOV ACC, DOWN
+
+@9
+MOV UP, RIGHT
+MOV UP, DOWN
+
+@10
+MOV LEFT, ACC
+NEG
+MOV ACC, DOWN

examples/segment20176/segment20176.cfg

@@ -0,0 +1,8 @@
+3 4
+CCCC
+CCCD
+CCCC
+I1 NUMERIC - 44 78 88 95
+I2 NUMERIC - 93 60 92 68
+O1 NUMERIC - -49 18 -4 27
+O2 NUMERIC - 49 -18 4 -27

src/TIS100/Sim/Run.hs

@@ -87,7 +87,8 @@ processComm (SimState (CPU.CPUState (CPU.CPUConfig rows cols) tiles_) ins_ outs_
     let (r, c) = CPU.position ptile
 
     case getRunState tile of
-      Tiles.WaitingOnRead p -> do
+      Tiles.WaitingOnRead _ (Just _) -> return (tiles, ins, outs)
+      Tiles.WaitingOnRead p Nothing -> do
         if r == 0 && p == Tiles.UP
           then do
             (maybeV, ins') <- readInputValue c ins
@@ -105,18 +106,18 @@ processComm (SimState (CPU.CPUState (CPU.CPUConfig rows cols) tiles_) ins_ outs_
             optile <- MV.read tiles o
             let otile = CPU.tile optile
             let op = Tiles.getOppositePort p
-            if readable op otile
-              then do
-                let (otile', val) = readValueFrom op otile
-                let maybeTile' = writeValueTo p (fromJust val) tile
+            let (otile', maybeVal) = readValueFrom op otile
+            case maybeVal of
+              Just val -> do
+                let maybeTile' = writeValueTo p val tile
                 case maybeTile' of
                   Just tile' -> do
                     MV.write tiles i $ ptile{CPU.tile = tile'}
                     MV.write tiles o $ optile{CPU.tile = otile'}
                     return (tiles, ins, outs)
                   Nothing -> return (tiles, ins, outs)
-              else return (tiles, ins, outs)
-      Tiles.WaitingOnWrite p -> do
+              Nothing -> return (tiles, ins, outs)
+      Tiles.WaitingOnWrite p pv -> do
         if r == rows - 1 && p == Tiles.DOWN
           then do
             let (tile', maybeV) = readValueFrom p tile
@@ -131,18 +132,14 @@ processComm (SimState (CPU.CPUState (CPU.CPUConfig rows cols) tiles_) ins_ outs_
             optile <- MV.read tiles o
             let otile = CPU.tile optile
             let op = Tiles.getOppositePort p
-            print $ "  Tile " ++ show o ++ " writable = " ++ show (writable op otile)
-            if writable op otile
-              then do
-                let (tile', val) = readValueFrom p tile
-                let maybeOtile' = writeValueTo op (fromJust val) otile
-                case maybeOtile' of
-                  Just otile' -> do
-                    MV.write tiles i $ ptile{CPU.tile = tile'}
-                    MV.write tiles o $ optile{CPU.tile = otile'}
-                    return (tiles, ins, outs)
-                  Nothing -> return (tiles, ins, outs)
-              else return (tiles, ins, outs)
+            let (tile', val) = readValueFrom p tile
+            let maybeOtile' = writeValueTo op (fromJust val) otile
+            case maybeOtile' of
+              Just otile' -> do
+                MV.write tiles i $ ptile{CPU.tile = tile'}
+                MV.write tiles o $ optile{CPU.tile = otile'}
+                return (tiles, ins, outs)
+              Nothing -> return (tiles, ins, outs)
       _ -> return (tiles, ins, outs)
 
   getOtherTile :: Int -> Tiles.Port' -> Int

src/TIS100/Tiles/Base.hs

@@ -19,8 +19,8 @@ instance Num Value where
 
 data RunState
   = Ready
-  | WaitingOnRead Port'
-  | WaitingOnWrite Port'
+  | WaitingOnRead Port' (Maybe Value)
+  | WaitingOnWrite Port' Value
   deriving (Eq, Show)
 
 data Port' = ANY | LAST | LEFT | RIGHT | UP | DOWN

src/TIS100/Tiles/ConnectedTile.hs

@@ -1,3 +1,5 @@
+{-# LANGUAGE InstanceSigs #-}
+
 module TIS100.Tiles.ConnectedTile where
 
 import TIS100.Tiles.Base (Port', Value)
@@ -7,12 +9,6 @@ class (Show t) => IsConnectedTile t where
   getRunState :: t -> Tiles.RunState
   setRunState :: Tiles.RunState -> t -> t
 
-  readable :: Port' -> t -> Bool
-  writable :: Port' -> t -> Bool
-
-  isWaitingOnRead :: t -> Maybe Port'
-  isWaitingOnWrite :: t -> Maybe Port'
-
   readValueFrom :: Port' -> t -> (t, Maybe Value)
   writeValueTo :: Port' -> Value -> t -> Maybe t
 
@@ -33,12 +29,6 @@ instance IsConnectedTile ConnectedTile where
   getRunState (ConnectedTile t) = getRunState t
   setRunState rs (ConnectedTile t) = ConnectedTile $ setRunState rs t
 
-  readable p (ConnectedTile t) = readable p t
-  writable p (ConnectedTile t) = writable p t
-
-  isWaitingOnRead (ConnectedTile t) = isWaitingOnRead t
-  isWaitingOnWrite (ConnectedTile t) = isWaitingOnWrite t
-
   readValueFrom p (ConnectedTile t) = (ConnectedTile t', v) where (t', v) = readValueFrom p t
   writeValueTo p v (ConnectedTile t) = ConnectedTile <$> writeValueTo p v t
 

src/TIS100/Tiles/Inactive.hs

@@ -10,12 +10,6 @@ instance IsConnectedTile InactiveTile where
   getRunState _ = Tiles.Ready
   setRunState _ _ = InactiveTile
 
-  readable _ _ = False
-  writable _ _ = False
-
-  isWaitingOnRead _ = Just Tiles.ANY
-  isWaitingOnWrite _ = Just Tiles.ANY
-
   readValueFrom _ t = (t, Nothing)
   writeValueTo _ _ t = Nothing