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cores/i2c: add a driver for the tca9548a i2c multiplexer
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# 2024 - LambdaConcept - [email protected] | ||
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from amaranth import * | ||
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from ...interface import stream | ||
from ..i2c.stream import * | ||
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__all__ = ["TCA9548A"] | ||
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class TCA9548A(Elaboratable): | ||
""" Driver for TCA9548A I2C multiplexer. | ||
On `self.ctrl` change, an I2C write is triggered to update | ||
the control register of the TCA9548A multiplexer: | ||
byte 0: i2c_addr | ||
byte 1: ctrl byte | ||
This module `source` stream is intented to be connected to an existing | ||
I2CStream instance through a stream arbiter. | ||
""" | ||
def __init__(self, i2c_addr=0x70): | ||
self.i2c_addr = i2c_addr | ||
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self.done = Signal() | ||
self.ctrl = Signal(8) | ||
self.source = stream.Endpoint(i2c_stream_description) | ||
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def elaborate(self, platform): | ||
source = self.source | ||
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m = Module() | ||
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init = Signal() | ||
ctrl_r = Signal.like(self.ctrl) | ||
ctrl_addr_n = Signal() | ||
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update = (self.ctrl != ctrl_r) | ||
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with m.FSM(): | ||
with m.State("IDLE"): | ||
with m.If(~init): | ||
m.d.sync += init.eq(1) | ||
m.next = "MUX" | ||
with m.Elif(update): | ||
m.d.sync += ctrl_r.eq(self.ctrl) | ||
m.next = "MUX" | ||
with m.Else(): | ||
m.d.comb += self.done.eq(1) | ||
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with m.State("MUX"): | ||
m.d.comb += [ | ||
source.r_wn .eq(0), # Write | ||
source.data .eq(Mux(~ctrl_addr_n, | ||
self.i2c_addr << 1, ctrl_r)), | ||
source.last .eq(ctrl_addr_n), | ||
source.valid.eq(1), | ||
] | ||
with m.If(source.valid & source.ready): | ||
m.d.sync += ctrl_addr_n.eq(~ctrl_addr_n) | ||
with m.If(source.last): | ||
m.next = "IDLE" | ||
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return m |