Digital adders coded in Verilog. They were synthesized to 45 nm TSMC library using Synopsys Design compiler in topographical mode. More details are available at the paper "A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design" (https://doi.org/10.1109/ICECS.2011.6122308).
- Carry-Ripple Adder (CRA)
- Carry-Select Adder (CSA)
- Carry-Lookahead Adder (CLA)
- Add-One Carry-Select Adder (A1CSA)
- Hierarchical Add-One Carry-Select Adder (A1CSAH)