Initial commit

.cargo/config

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+[build]
+target = 'thumbv7em-none-eabi'
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = 'arm-none-eabi-gdb'
+rustflags = [
+  "-C", "link-arg=-Tlink.x",
+]

.gdbinit

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+# disable "are you sure you want to quit?"
+define hook-quit
+    set confirm off
+end
+
+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# set backtrace limit to not have infinite backtrace loops
+set backtrace limit 32
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+load
+cont

.gitignore

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+target
+Cargo.lock

.travis.yml

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+language: rust
+rust:
+  - 1.33.0
+  - stable
+  - nightly
+cache: cargo
+sudo: false
+env:
+  global:
+    - RUSTFLAGS="--deny warnings"
+    - RUST_BACKTRACE=1
+    - CARGO_INCREMENTAL=0  # decrease size of `target` to make the cache smaller
+  matrix:
+    - FEATURES=""  # default configuration
+    - FEATURES="--all-features"
+script:
+  - cargo build --all --examples $FEATURES
+  - cargo build --all --examples --release $FEATURES
+notifications:
+  email:
+    on_success: never

CHANGELOG.md

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+# Changelog
+
+## Unreleased
+
+Initial release.

Cargo.toml

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+[package]
+name = "spi-memory"
+version = "0.0.0"
+authors = ["Jonas Schievink <[email protected]>"]
+edition = "2018"
+description = "A generic driver for different SPI Flash and EEPROM chips"
+documentation = "https://docs.rs/spi-memory/"
+repository = "https://github.com/jonas-schievink/spi-memory.git"
+keywords = ["embedded-hal-driver", "serial", "flash", "eeprom", "spi"]
+categories = ["embedded"]
+readme = "README.md"
+license = "0BSD"
+
+[dependencies]
+embedded-hal = "0.2.3"
+log = { version = "0.4.6", optional = true }
+bitflags = "1.0.4"
+
+[dev-dependencies]
+cortex-m = "0.6.0"
+cortex-m-rt = "0.6.8"
+cortex-m-semihosting = "0.3.3"
+stm32f4xx-hal = { version = "0.5.0", features = ["stm32f401"] }
+panic-semihosting = "0.5.2"
+
+[profile.dev]
+opt-level = "z"
+panic = "abort"
+
+# cargo-release configuration
+[package.metadata.release]
+tag-message = "{{version}}"
+no-dev-version = true
+pre-release-commit-message = "Release {{version}}"
+
+# Change the changelog's `Unreleased` section to refer to this release and
+# prepend new `Unreleased` section
+[[package.metadata.release.pre-release-replacements]]
+file    = "CHANGELOG.md"
+search  = "## Unreleased"
+replace = "## Unreleased\n\nNo changes.\n\n## {{version}} - {{date}}"
+
+# Bump the version inside the example manifest in `README.md`
+[[package.metadata.release.pre-release-replacements]]
+file    = "README.md"
+search  = 'spi-memory = "[a-z0-9\\.-]+"'
+replace = 'spi-memory = "{{version}}"'
+
+# Bump the version referenced by the `html_root_url` attribute in `lib.rs`
+[[package.metadata.release.pre-release-replacements]]
+file    = "src/lib.rs"
+search  = "https://docs.rs/spi-memory/[a-z0-9\\.-]+"
+replace = "https://docs.rs/spi-memory/{{version}}"

LICENSE

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+Copyright (C) Jonas Schievink <[email protected]>
+
+Permission to use, copy, modify, and/or distribute this software for
+any purpose with or without fee is hereby granted.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

README.md

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+# `spi-memory`
+
+[![crates.io](https://img.shields.io/crates/v/spi-memory.svg)](https://crates.io/crates/spi-memory)
+[![docs.rs](https://docs.rs/spi-memory/badge.svg)](https://docs.rs/spi-memory/)
+[![Build Status](https://travis-ci.org/jonas-schievink/spi-memory.svg?branch=master)](https://travis-ci.org/jonas-schievink/spi-memory)
+
+This crate provides a generic [`embedded-hal`]-based driver for different
+families of SPI Flash and EEPROM chips.
+
+Right now, only 25-series Flash chips are supported. Feel free to send PRs to
+support other families though!
+
+Please refer to the [changelog](CHANGELOG.md) to see what changed in the last
+releases.
+
+[`embedded-hal`]: https://github.com/rust-embedded/embedded-hal
+
+## Usage
+
+Add an entry to your `Cargo.toml`:
+
+```toml
+[dependencies]
+spi-memory = "0.0.0"
+```
+
+Check the [API Documentation](https://docs.rs/spi-memory/) for how to use the
+crate's functionality.

RELEASE_PROCESS.md

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+# What to do to publish a new release
+
+1. Ensure all notable changes are in the changelog under "Unreleased".
+
+2. Execute `cargo release <level>` to bump version(s), tag and publish
+   everything. External subcommand, must be installed with `cargo install
+   cargo-release`.
+
+   `<level>` can be one of `major|minor|patch`. If this is the first release
+   (`0.1.0`), use `minor`, since the version start out as `0.0.0`.
+
+3. Go to the GitHub releases, edit the just-pushed tag. Copy the release notes
+   from the changelog.

examples/dump.rs

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+//! A Nucleo-64 F401 example that dumps flash contents to a USART.
+//!
+//! The flash chip is connected to the canonical SPI port on the Arduino-style
+//! connector:
+//!
+//! *  SCK = D13 = PA5
+//! * MISO = D12 = PA6
+//! * MOSI = D11 = PA7
+//!
+//! The data is dumped in hexadecimal format through USART2 (TX = D1 = PA2).
+
+#![no_std]
+#![no_main]
+
+extern crate panic_semihosting;
+
+use cortex_m_rt::entry;
+use stm32f4xx_hal::spi::Spi;
+use stm32f4xx_hal::stm32 as pac;
+use stm32f4xx_hal::gpio::GpioExt;
+use stm32f4xx_hal::time::{Bps, MegaHertz};
+use stm32f4xx_hal::rcc::RccExt;
+use stm32f4xx_hal::serial::{self, Serial};
+use embedded_hal::spi::MODE_0;
+use embedded_hal::digital::v2::OutputPin;
+use embedded_hal::serial::Write;
+use cortex_m_semihosting::hprintln;
+
+use spi_memory::series25::Flash;
+
+use core::fmt::Write as _;
+
+/// Flash chip size in Mbit.
+const MEGABITS: u32 = 4;
+
+/// Serial baudrate.
+const BAUDRATE: u32 = 912600;
+
+/// Size of the flash chip in bytes.
+const SIZE_IN_BYTES: u32 = (MEGABITS * 1024 * 1024) / 8;
+
+
+fn print<'a, E>(buf: &[u8], w: &'a mut (dyn Write<u8, Error=E> + 'static)) {
+    for c in buf {
+        write!(w, "{:02X}", c).unwrap();
+    }
+    writeln!(w).unwrap();
+}
+
+#[entry]
+fn main() -> ! {
+    let periph = pac::Peripherals::take().unwrap();
+    let clocks = periph.RCC.constrain().cfgr.freeze();
+    let gpioa = periph.GPIOA.split();
+
+    let cs = {
+        let mut cs = gpioa.pa9.into_push_pull_output();
+        cs.set_high().unwrap();  // deselect
+        cs
+    };
+
+    let spi = {
+        let sck = gpioa.pa5.into_alternate_af5();
+        let miso = gpioa.pa6.into_alternate_af5();
+        let mosi = gpioa.pa7.into_alternate_af5();
+
+        Spi::spi1(periph.SPI1, (sck, miso, mosi), MODE_0, MegaHertz(1).into(), clocks)
+    };
+
+    let mut serial = {
+        let tx = gpioa.pa2.into_alternate_af7();
+
+        let config = serial::config::Config {
+            baudrate: Bps(BAUDRATE),
+            ..Default::default()
+        };
+        Serial::usart2(periph.USART2, (tx, serial::NoRx), config, clocks).unwrap()
+    };
+
+    let mut flash = Flash::init(spi, cs).unwrap();
+    let id = flash.read_jedec_id().unwrap();
+    hprintln!("{:?}", id).ok();
+
+    let mut addr = 0;
+    const BUF: usize = 32;
+    let mut buf = [0; BUF];
+
+    while addr < SIZE_IN_BYTES {
+        flash.read(addr, &mut buf).unwrap();
+        print(&buf, &mut serial);
+
+        addr += BUF as u32;
+    }
+
+    hprintln!("DONE").ok();
+
+    loop {}
+}

memory.x

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+MEMORY
+{
+  /* NOTE K = KiBi = 1024 bytes */
+  FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+  RAM : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);

src/lib.rs

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+//! An `embedded-hal`-based SPI-Flash chip driver.
+//!
+//! This crate aims to be compatible with common families of SPI flash chips.
+//! Currently, reading 25-series chips is supported, and support for writing and
+//! erasing as well as other chip families (eg. 24-series chips) is planned.
+//! Contributions are always welcome!
+
+#![doc(html_root_url = "https://docs.rs/spi-memory/0.0.0")]
+#![warn(missing_debug_implementations, rust_2018_idioms)]
+#![no_std]
+
+#[macro_use]
+mod log;
+pub mod series25;
+mod utils;
+
+use core::fmt::{self, Debug};
+use embedded_hal::blocking::spi::Transfer;
+use embedded_hal::digital::v2::OutputPin;
+
+mod private {
+    #[derive(Debug)]
+    pub enum Private {}
+}
+
+/// The error type used by this library.
+///
+/// This can encapsulate an SPI or GPIO error, and adds its own protocol errors
+/// on top of that.
+pub enum Error<SPI: Transfer<u8>, GPIO: OutputPin> {
+    /// An SPI transfer failed.
+    Spi(SPI::Error),
+
+    /// A GPIO could not be set.
+    Gpio(GPIO::Error),
+
+    /// Status register contained unexpected flags.
+    ///
+    /// This can happen when the chip is faulty, incorrectly connected, or the
+    /// driver wasn't constructed or destructed properly (eg. while there is
+    /// still a write in progress).
+    UnexpectedStatus,
+
+    #[doc(hidden)]
+    __NonExhaustive(private::Private),
+}
+
+impl<SPI: Transfer<u8>, GPIO: OutputPin> Debug for Error<SPI, GPIO>
+where
+    SPI::Error: Debug,
+    GPIO::Error: Debug,
+{
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Error::Spi(spi) => write!(f, "Error::Spi({:?})", spi),
+            Error::Gpio(gpio) => write!(f, "Error::Gpio({:?})", gpio),
+            Error::UnexpectedStatus => f.write_str("Error::UnexpectedStatus"),
+            Error::__NonExhaustive(_) => unreachable!(),
+        }
+    }
+}