VerilogNotes

Notes for a Tutorial on Verilog that I have been posting on YouTube.

Useful Documentation Links

Ice40 FPGAs

https://www.latticesemi.com/Products/FPGAandCPLD/iCE40

Useful Verilog Documentation

• IEEE 1364 Standards
  • 1364-2005 - IEEE Standard for Verilog Hardware Description Language
  • 1364.1-2002 - IEEE Standard for Verilog Register Transfer Level Synthesis
• By Pong P. Chu
  • FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version 1st Edition
  • FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition (The next edition of the above Verilog Examples book.)
  • SystemVerilog Vs Verilog in RTL Design - Pong P. Chu (This looks like an intro/summary of the above SystemVerilog book.)
• The Clifford E. Cummings Cliff-Notes on Verilog and SystemVerilog include these:
  • Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
  • "full_case parallel_case", the Evil Twins of Verilog Synthesis
• Yosys
  • Yosys Open SYnthesis Suite (This is the compiler I use in my tutorial.)
  • Yosys Documentation including the YosysHQ Yosys Manual.
• https://en.wikipedia.org/wiki/Verilog

Many Universities tend to leave copies of IEEE standards laying around for the world to see. Find one for yourself: https://www.google.com/search?q=1364-2005+pdf

System Verilog Documents

• http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf

Other YouTube Resources

Peter Mathy's YouTube series on Verilog: https://www.youtube.com/user/mathys2000yt/videos He uses an older style module declaration (akin to the K&R vs ANSI C function definition styles.) I prefer the modern style where we need not type the names of the ports twice.

• https://www.youtube.com/watch?v=0age83XI8Z4
• https://www.youtube.com/watch?v=IREjtgG33hQ
• https://www.youtube.com/watch?v=yr3Hk8Cnl3Y
• https://www.youtube.com/watch?v=311tqcyJ2SQ
• https://youtu.be/wf-QMMsj850
• https://www.youtube.com/watch?v=f7DSYhEGXFA