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Pedals
The pedal situation might be complicated. The pedal board is intended to be sort of vague.
Here's a snippet of some pedal-related circuitry I found.
http://web.archive.org/web/20110828064336/http://tomscarff.110mb.com/foot_pedal/foot_pedal_cct.GIF
As it stands, the pedal board just has a many-channel ADC and the appropriate physical interface for standard digital piano pedals. The ADC can be polled by the main board as frequently (or infrequently) as the main board would like. But the pedal doesn't actually move frequently, compared to the possible polling frequencies. Simple ADCs have no capacity to detect or act on meaningful changes, so we're left with scanning.
We could imagine an improved pedal board, which replaces the generic I2C ADC with a small microprocessor capable of reading multiple ADC channels, and generating interrupts for the main board based on an understanding of what/how the pedals behave. And while we'd like to support continuous pedals, 8 bits of pedal resolution per pedal is simply unnecessary. Some pedals don't have continuous behavior, and the ones that do probably need closer to 4-5 bits of resolution, especially if we can clean up any nonlinearities in the signal before passing the values along.
Since the intention of this project is to integrate with standard piano mechanics, we've got an opportunity to implement something present in only a few of the highest-end hybrid digital pianos. That's the interaction of the damper pedal, and the feel of the keys. When the damper pedal of a grand is depressed, it should take very slightly less force to depress the keys, as you're not having to lift the damper. A very advanced pedal board could not only measure the position of the pedal, but also control a servo motor which would lift faux damper weights from every key.
As a note to myself, the STM32L031F6P6 looks like the most appropriate part. It is cheaper than the currently selected ADC, is available in a TSSOP20 package (slightly less intimidating to solder), has I2C, and can trade off between 4-8 ADC channels and 1-3 timers with PWM output. It has a few GPIO left over after all of that. As L series, it'll run at low voltages, and has very low power demands. The only downside is that it will require programming, which can't be performed by the main board over the I2C interface. It can be done via USART2, though. The PA9/PA10 pins could be safely brought out to an FTDI header that can also supply the +3.3V necessary for standalone reprogramming.