Improve documentation

README.md

@@ -1,41 +1,11 @@
 ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg)
 
-# Tiny Tapeout Verilog Project Template
+# Time-to-Digital Converter (TDC)
 
-- [Read the documentation for project](docs/info.md)
+## Copyright 2024 by Harald Pretl, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria
 
-## What is Tiny Tapeout?
+A TDC is implemented in Verilog and synthesized, with a configurable delay length, and based on an interleaved inverter chain.
 
-TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.
+The result of the delay line capture is output directly, without any bubble correction or coding.
 
-To learn more and get started, visit https://tinytapeout.com.
-
-## Verilog Projects
-
-1. Add your Verilog files to the `src` folder.
-2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
-3. Edit [docs/info.md](docs/info.md) and add a description of your project.
-4. Optionally, add a testbench to the `test` folder. See [test/README.md](test/README.md) for more information.
-
-The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
-
-## Enable GitHub actions to build the results page
-
-- [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part)
-
-## Resources
-
-- [FAQ](https://tinytapeout.com/faq/)
-- [Digital design lessons](https://tinytapeout.com/digital_design/)
-- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)
-- [Join the community](https://tinytapeout.com/discord)
-- [Build your design locally](https://docs.google.com/document/d/1aUUZ1jthRpg4QURIIyzlOaPWlmQzr-jBn3wZipVUPt4)
-
-## What next?
-
-- [Submit your design to the next shuttle](https://app.tinytapeout.com/).
-- Edit [this README](README.md) and explain your design, how it works, and how to test it.
-- Share your project on your social network of choice:
-  - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/)
-  - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn)
-  - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@matthewvenn](https://twitter.com/matthewvenn)
+This implementation shall allow to study the bubble signatures which are happening, and will allow to develop a proper bubble correction logic. In addition, the DNL and INL of the TDC can be quantified.

info.yaml

@@ -1,53 +1,54 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  title:        "Synthesized Time-to-Digital Converter (TDC)"
+  author:       "Harald Pretl"
+  discord:      "hpretl"
+  description:  "Synthesized TDC based on an interleaved delay line"
+  language:     "Verilog"
+  clock_hz:     50000000 # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_hpretl_tt06_tdc"
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:        
-    - "project.v"
+    - "tt_um_hpretl_tt06_tdc.v"
+    - "tdc.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "Start signal of TDC"
+  ui[1]: "n.u."
+  ui[2]: "n.u."
+  ui[3]: "n.u."
+  ui[4]: "output select"
+  ui[5]: "output select"
+  ui[6]: "output select"
+  ui[7]: "output select"
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[0]: "Result LSB"
+  uo[1]: "Result"
+  uo[2]: "Result"
+  uo[3]: "Result"
+  uo[4]: "Result"
+  uo[5]: "Result"
+  uo[6]: "Result"
+  uo[7]: "Result MSB"
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "n.u."
+  uio[1]: "n.u."
+  uio[2]: "n.u."
+  uio[3]: "n.u."
+  uio[4]: "n.u."
+  uio[5]: "n.u."
+  uio[6]: "n.u."
+  uio[7]: "n.u."
 
 # Do not change!
 yaml_version: 6

sim/user_config.tcl

@@ -0,0 +1,11 @@
+# Set design name
+set ::env(DESIGN_NAME) "tt_um_hpretl_tt06_tdc"
+# Set Verilog source files
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/tt_um_hpretl_tt06_tdc.v]
+# Interpret instantiated SKY130-Standardcells as blackbox
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+# Rexeg to flag nets where buffers are not allowed (analog signals)
+# No linting
+set ::env(QUIT_ON_SYNTH_CHECKS) 0
+# Set die area
+set ::env(DIE_AREA) "0 0 100 100"