Skip to content

Commit

Permalink
prepare wasm support for aarch64 and riscv64
Browse files Browse the repository at this point in the history
  • Loading branch information
stlankes committed Jun 22, 2024
1 parent 3d83f6c commit 313122f
Show file tree
Hide file tree
Showing 8 changed files with 90 additions and 3 deletions.
3 changes: 2 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,6 @@ talc = { version = "4" }
time = { version = "0.3", default-features = false }
volatile = { version = "0.6", features = ["unstable"] }
zerocopy = { version = "0.7", default-features = false }
wasmtime = { version = "22.0", default-features = false, features = ["runtime", "gc", "component-model"], optional = true }

[dependencies.smoltcp]
version = "0.11"
Expand Down Expand Up @@ -138,12 +137,14 @@ multiboot = "0.8"
uart_16550 = "0.3"
x86 = { version = "0.52", default-features = false }
x86_64 = "0.15"
wasmtime = { version = "22.0", default-features = false, features = ["runtime", "gc", "component-model"], optional = true }

[target.'cfg(target_arch = "aarch64")'.dependencies]
aarch64 = { version = "0.0.10", default-features = false }
arm-gic = { version = "0.1" }
hermit-dtb = { version = "0.1" }
semihosting = { version = "0.1", optional = true }
wasmtime = { version = "22.0", default-features = false, features = ["runtime", "gc", "component-model"], optional = true }

[target.'cfg(target_arch = "riscv64")'.dependencies]
riscv = "0.11"
Expand Down
18 changes: 18 additions & 0 deletions src/arch/aarch64/kernel/longjmp.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
# The code is derived from the musl implementation
# of longjmp.
.section .text
.global longjmp
longjmp:
# IHI0055B_aapcs64.pdf 5.1.1, 5.1.2 callee saved registers
ldp x19, x20, [x0,#0]
ldp x21, x22, [x0,#16]
ldp x23, x24, [x0,#32]
ldp x25, x26, [x0,#48]
ldp x27, x28, [x0,#64]
ldp x29, x30, [x0,#80]
ldr x2, [x0,#104]
mov sp, x2

cmp w1, 0
csinc w0, w1, wzr, ne
br x30
3 changes: 3 additions & 0 deletions src/arch/aarch64/kernel/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,9 @@ use crate::arch::aarch64::kernel::serial::SerialPort;
use crate::arch::aarch64::mm::{PhysAddr, VirtAddr};
use crate::env;

global_asm!(include_str!("setjmp.s"));
global_asm!(include_str!("longjmp.s"));

const SERIAL_PORT_BAUDRATE: u32 = 115200;

static mut COM1: SerialPort = SerialPort::new(0x800);
Expand Down
16 changes: 16 additions & 0 deletions src/arch/aarch64/kernel/setjmp.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
# The code is derived from the musl implementation
# of setjmp.
.section .text
.global setjmp
setjmp:
# IHI0055B_aapcs64.pdf 5.1.1, 5.1.2 callee saved registers
stp x19, x20, [x0,#0]
stp x21, x22, [x0,#16]
stp x23, x24, [x0,#32]
stp x25, x26, [x0,#48]
stp x27, x28, [x0,#64]
stp x29, x30, [x0,#80]
mov x2, sp
str x2, [x0,#104]
mov x0, #0
ret
23 changes: 23 additions & 0 deletions src/arch/riscv64/kernel/longjmp.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
# The code is derived from the musl implementation
# of longjmp.
.section .text
.global longjmp
longjmp:
ld s0, 0(a0)
ld s1, 8(a0)
ld s2, 16(a0)
ld s3, 24(a0)
ld s4, 32(a0)
ld s5, 40(a0)
ld s6, 48(a0)
ld s7, 56(a0)
ld s8, 64(a0)
ld s9, 72(a0)
ld s10, 80(a0)
ld s11, 88(a0)
ld sp, 96(a0)
ld ra, 104(a0)

seqz a0, a1
add a0, a0, a1
ret
4 changes: 4 additions & 0 deletions src/arch/riscv64/kernel/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ pub mod switch;
pub mod systemtime;

use alloc::vec::Vec;
use core::arch::global_asm;
use core::ptr;
use core::sync::atomic::{AtomicPtr, AtomicU32, AtomicU64, Ordering};

Expand All @@ -27,6 +28,9 @@ use crate::arch::riscv64::mm::{physicalmem, PhysAddr, VirtAddr};
use crate::config::KERNEL_STACK_SIZE;
use crate::env;

global_asm!(include_str!("setjmp.s"));
global_asm!(include_str!("longjmp.s"));

// Used to store information about available harts. The index of the hart in the vector
// represents its CpuId and does not need to match its hart_id
pub static mut HARTS_AVAILABLE: Vec<usize> = Vec::new();
Expand Down
22 changes: 22 additions & 0 deletions src/arch/riscv64/kernel/setjmp.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
# The code is derived from the musl implementation
# of setjmp.
.section .text
.global setjmp
setjmp:
sd s0, 0(a0)
sd s1, 8(a0)
sd s2, 16(a0)
sd s3, 24(a0)
sd s4, 32(a0)
sd s5, 40(a0)
sd s6, 48(a0)
sd s7, 56(a0)
sd s8, 64(a0)
sd s9, 72(a0)
sd s10, 80(a0)
sd s11, 88(a0)
sd sp, 96(a0)
sd ra, 104(a0)

li a0, 0
ret
4 changes: 2 additions & 2 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,7 @@ mod shell;
mod synch;
pub mod syscalls;
pub mod time;
#[cfg(all(target_arch = "x86_64", feature = "wasm"))]
#[cfg(all(any(target_arch = "x86_64", target_arch = "aarch64"), feature = "wasm"))]
mod wasm;

#[cfg(target_os = "none")]
Expand Down Expand Up @@ -158,7 +158,7 @@ extern "C" fn initd(_arg: usize) {
#[cfg(not(test))]
let (argc, argv, environ) = syscalls::get_application_parameters();

#[cfg(all(target_arch = "x86_64", feature = "wasm"))]
#[cfg(all(any(target_arch = "x86_64", target_arch = "aarch64"), feature = "wasm"))]
if crate::wasm::init().is_err() {
error!("Unable to initialized wasm support")
}
Expand Down

0 comments on commit 313122f

Please sign in to comment.