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add tests for U types #17

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Jan 10, 2024
Merged

add tests for U types #17

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3 changes: 3 additions & 0 deletions src/asm/out/utypes.memh
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@@ -0,0 +1,3 @@
fffff0b7 // PC=0x0 line=1: lui x1, 1048575 # x1 = 32'b11111111111111111111000000000000
00008093 // PC=0x4 line=2: addi x1, x1, 0 # nop
fffff117 // PC=0x8 line=3: auipc x2, 1048575 # x2 = 32'b11111111111111111111000000001000
50 changes: 50 additions & 0 deletions src/asm/test/utypes.result
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Usage:
./rv32_simulator +initial_memory=path/to/memh/file
Additional arguments:
+initial_memory=path/to/memh/file
Required: path to a memh file that containes the assembled binary to run.
+max_cycles=NUMBER_OF_CYCLES_TO_RUN
+wave_fn=path/to/wave/file
default is rv32_simulator.fst
+final_memory=path/to/memh/file
If provided, the final memory contents will be saved here. Use this to debug your store instructions.
WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/utypes.memh): Not enough words in the file for the requested range [0:1023].
Running simulation of memory ../asm/out/utypes.memh for up to 10000 cycles. Waves will be stored to rv32_simulator.fst.
FST info: dumpfile rv32_simulator.fst opened for output.
Ran 10000 cycles, finishing.
#TESTASSERTOUTPUT|---------------------------------------|
#TESTASSERTOUTPUT| Register File State :) |
#TESTASSERTOUTPUT|---------------------------------------|
#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x01, ra = 0xfffff000 ( -4096)|
#TESTASSERTOUTPUT| x02, sp = 0xfffff008 ( -4088)|
#TESTASSERTOUTPUT| x03, gp = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x04, tp = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x05, t0 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x06, t1 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x07, t2 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x10, a0 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x11, a1 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x13, a3 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x14, a4 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x18, s2 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x19, s3 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x20, s4 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT|---------------------------------------|
40 changes: 40 additions & 0 deletions src/asm/utypes.s
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lui x1, 1048575 # x1 = 32'b11111111111111111111000000000000
addi x1, x1, 0 # nop
auipc x2, 1048575 # x2 = 32'b11111111111111111111000000001000

#TESTASSERTOUTPUT|---------------------------------------|
#TESTASSERTOUTPUT| Register File State :) |
#TESTASSERTOUTPUT|---------------------------------------|
#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x01, ra = 0xfffff000 ( -4096)|
#TESTASSERTOUTPUT| x02, sp = 0xfffff008 ( -4088)|
#TESTASSERTOUTPUT| x03, gp = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x04, tp = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x05, t0 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x06, t1 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x07, t2 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x10, a0 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x11, a1 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x13, a3 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x14, a4 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x18, s2 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x19, s3 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x20, s4 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)|
#TESTASSERTOUTPUT|---------------------------------------|
3 changes: 2 additions & 1 deletion src/components/Makefile
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Expand Up @@ -106,10 +106,11 @@ rv32_simulator: tests/provided/rv32_simulator.sv src/**/*.sv
node ../asm/validate.js $(basename $<).s test/$<

test_rv32_ir_types: addi.validate itypes.validate irtypes.validate
test_rv32_utypes: utypes.validate
test_rv32_branch: beq.validate bne.validate blt.validate bge.validate bgeu.validate bltu.validate
test_rv32_jal: jal_jalr.validate

test_rv32_all: test_rv32_ir_types storeload.validate test_rv32_branch test_rv32_jal
test_rv32_all: test_rv32_ir_types storeload.validate test_rv32_branch test_rv32_jal test_rv32_utypes

# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
# Instruction Type Tests
Expand Down
44 changes: 42 additions & 2 deletions src/components/src/cpu/rv32i_multicycle_core.sv
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Expand Up @@ -35,7 +35,8 @@ module rv32i_multicycle_core(
S_ALUWB = 6,
S_MEMWRITE = 7,
S_BRANCH = 8,
S_JALR = 9
S_JALR = 9,
S_UIPC = 10
} state;

/* ---------------------- Standard Control Signals ---------------------- */
Expand Down Expand Up @@ -123,7 +124,13 @@ module rv32i_multicycle_core(


/* ---------------------- Result SRC Signals ---------------------- */
enum logic [1:0] {RESULT_SRC_ALU, RESULT_SRC_MEM_DATA, RESULT_SRC_ALU_LAST, RESULT_SRC_PC_NEXT_INSTRUCTION} result_src;
enum logic [2:0] {
RESULT_SRC_ALU,
RESULT_SRC_MEM_DATA,
RESULT_SRC_ALU_LAST,
RESULT_SRC_PC_NEXT_INSTRUCTION,
RESULT_SRC_IMMEDIATE
} result_src;
logic [31:0] result;

always_comb begin : result_signals
Expand All @@ -132,6 +139,7 @@ module rv32i_multicycle_core(
RESULT_SRC_MEM_DATA: result = mem_data;
RESULT_SRC_ALU_LAST: result = alu_last;
RESULT_SRC_PC_NEXT_INSTRUCTION: result = PC_next_instruction;
RESULT_SRC_IMMEDIATE: result = extended_immediate;
endcase
end

Expand Down Expand Up @@ -346,6 +354,25 @@ module rv32i_multicycle_core(
/* -------------------------------------------------------------------------------------------------------------------*/
/* DATAPATH for RI (end) */
/* -------------------------------------------------------------------------------------------------------------------*/


/* -------------------------------------------------------------------------------------------------------------------*/
/* DATAPATH for auipc (begin) */
/* -------------------------------------------------------------------------------------------------------------------*/
always_comb begin: auipc_datapath
case(state)
S_UIPC: begin
set_default;
alu_control = ALU_ADD;
alu_src_a = ALU_SRC_A_PC;
alu_src_b = ALU_SRC_B_IMM;
alu_last_ena = 1;
end
endcase
end
/* -------------------------------------------------------------------------------------------------------------------*/
/* DATAPATH for auipc (end) */
/* -------------------------------------------------------------------------------------------------------------------*/

/* -------------------------------------------------------------------------------------------------------------------*/
/* DATAPATH for ALU WB (begin) */
Expand All @@ -369,6 +396,10 @@ module rv32i_multicycle_core(
result_src = RESULT_SRC_PC_NEXT_INSTRUCTION;
pc_next_src = PC_NEXT_JUMP;
end
`OP_U_IPC: begin
result_src = RESULT_SRC_ALU_LAST;
pc_next_src = PC_NEXT_INSTRUCTION;
end
endcase
end
endcase
Expand Down Expand Up @@ -396,6 +427,12 @@ module rv32i_multicycle_core(
alu_src_a = ALU_SRC_A_OLD_PC;
alu_src_b = ALU_SRC_B_IMM;
end
`OP_U_LUI: begin
result_src = RESULT_SRC_IMMEDIATE;
reg_write = 1;
pc_next_src = PC_NEXT_INSTRUCTION;
PC_ena = 1;
end
endcase
end
endcase
Expand Down Expand Up @@ -492,15 +529,18 @@ module rv32i_multicycle_core(
S_DECODE: begin
case(op)
`OP_I_LOAD: state <= S_MEMADR;
`OP_U_LUI: state <= S_FETCH;
`OP_I_STORE: state <= S_MEMADR;
`OP_IMMEDIATE_I_EXECUTE: state <= S_EXECUTE_RI;
`OP_R_EXECUTE: state <= S_EXECUTE_RI;
`OP_U_IPC: state <= S_UIPC;
`OP_BRANCH: state <= S_BRANCH;
`OP_JAL: state <= S_ALUWB;
`OP_JALR: state <= S_JALR;
endcase
end
S_EXECUTE_RI: state <= S_ALUWB;
S_UIPC: state <= S_ALUWB;
S_JALR : state <= S_ALUWB;
S_ALUWB: state <= S_FETCH;
S_MEMADR: begin
Expand Down