fix bug

hazel-sudz · Jan 10, 2024 · c174d14 · c174d14
1 parent c11ce4a
commit c174d14
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Showing 2 changed files with 12 additions and 8 deletions.
diff --git a/src/components/src/cpu/register_file.sv b/src/components/src/cpu/register_file.sv
@@ -52,7 +52,7 @@ module register_file(rst, clk, wr_ena, wr_addr, wr_data, rd_addr0, rd_data0, rd_
         for(i=1;i<32;i++) begin
             register #(32) REG(
                 .clk(clk), 
-                .ena(write_addr_decoded[i]), 
+                .ena(write_addr_decoded[i] & wr_ena), 
                 .rst(rst), 
                 .d(wr_data),
                 .q(xn[i]));

diff --git a/src/components/tests/our/test_register_file.sv b/src/components/tests/our/test_register_file.sv
@@ -43,19 +43,23 @@ module test_register_file;
                 wr_addr = i;
                 wr_data_gen = $random();
                 wr_data = wr_data_gen;
-                #1; 
                 @(posedge clk);
 
-                // read from register
+                 // test to make sure enable works correctly
+                @(negedge clk);
                 wr_ena = 0;
-                rd_addr0 = i;
-                rd_addr1 = i;
-
-                // test to make sure enable works correctly
                 wr_data = $random();
+                wr_addr = i;
+                @(posedge clk);
 
-                #5;
+                // test reading from register
+                @(negedge clk);
+                wr_ena = 0;
+                rd_addr0 = i;
+                rd_addr1 = i;
+                #1;
 
+
                 // check value of register
                 $display("[register_file]: [rd_addr0: %0d], [rd_data0: %0d], [rd_addr1: %0d], [rd_data1: %0d], [exp_rd_data0: %0d]", rd_addr0, rd_data1, rd_addr1, rd_data1, wr_data);
                 assert(wr_data_gen == rd_data0) else $fatal;