add beq and bne test

hazel-sudz · Jan 10, 2024 · 6ae5d05 · 6ae5d05
1 parent 188b66a
commit 6ae5d05
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Showing 12 changed files with 252 additions and 21 deletions.
diff --git a/src/asm/beq.s b/src/asm/beq.s
@@ -1,9 +1,47 @@
 addi  x1, x0, 5            # x01 = 5
 
-addi    x8, x0, 0           # x08 = 0
-loop_head:
-addi    x8, x8, 1           # x08 ++
-beq     x8, x1, loop_end
-beq     x0, x0, loop_head
-loop_end:
-                            # x08 = 5
+addi    x2, x0, 0           # x02 = 0
+loop_head_beq:
+addi    x2, x2, 1           # x02 ++
+beq     x2, x1, trap
+beq     x0, x0, loop_head_beq
+                            # x02 = 5
+
+trap:
+
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT| Register File State :)                |
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x01, ra = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x03, gp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x12, a2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x13, a3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x14, a4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x15, a5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x16, a6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x17, a7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x18, s2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x19, s3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x20, s4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x21, s5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|---------------------------------------|
diff --git a/src/asm/bne.s b/src/asm/bne.s
@@ -0,0 +1,47 @@
+addi  x1, x0, 5             # x01 = 5
+
+addi    x2, x0, 0           # x02 = 0
+loop_head_bneq:
+addi    x2, x2, 1           # x02 ++
+bne     x2, x1, loop_head_bneq
+beq     x0, x0, trap
+                            # x02 = 4
+
+trap:
+
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT| Register File State :)                |
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x01, ra = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x03, gp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x12, a2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x13, a3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x14, a4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x15, a5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x16, a6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x17, a7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x18, s2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x19, s3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x20, s4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x21, s5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|---------------------------------------|
diff --git a/src/asm/out/beq.memh b/src/asm/out/beq.memh
@@ -1,5 +1,5 @@
 00500093 // PC=0x0 line=1: addi  x1, x0, 5            # x01 = 5
-00000413 // PC=0x4 line=3: addi    x8, x0, 0           # x08 = 0
-00140413 // PC=0x8 line=5: addi    x8, x8, 1           # x08 ++
-00140463 // PC=0xc line=6: beq     x8, x1, loop_end
-fe000ce3 // PC=0x10 line=7: beq     x0, x0, loop_head
+00000113 // PC=0x4 line=3: addi    x2, x0, 0           # x02 = 0
+00110113 // PC=0x8 line=5: addi    x2, x2, 1           # x02 ++
+00110463 // PC=0xc line=6: beq     x2, x1, trap
+fe000ce3 // PC=0x10 line=7: beq     x0, x0, loop_head_beq
diff --git a/src/asm/out/bne.memh b/src/asm/out/bne.memh
@@ -0,0 +1,5 @@
+00500093 // PC=0x0 line=1: addi  x1, x0, 5             # x01 = 5
+00000113 // PC=0x4 line=3: addi    x2, x0, 0           # x02 = 0
+00110113 // PC=0x8 line=5: addi    x2, x2, 1           # x02 ++
+fe111ee3 // PC=0xc line=6: bne     x2, x1, loop_head_bneq
+00000263 // PC=0x10 line=7: beq     x0, x0, trap
diff --git a/src/asm/out/branch.memh b/src/asm/out/branch.memh
@@ -0,0 +1,9 @@
+00500093 // PC=0x0 line=1: addi  x1, x0, 5            # x01 = 5
+00000113 // PC=0x4 line=3: addi    x2, x0, 0           # x02 = 0
+00110113 // PC=0x8 line=5: addi    x2, x2, 1           # x02 ++
+00110c63 // PC=0xc line=6: beq     x2, x1, trap
+fe000ce3 // PC=0x10 line=7: beq     x0, x0, loop_head_beq
+00000193 // PC=0x14 line=10: addi    x3, x0, 0           # x03 = 0
+00118193 // PC=0x18 line=12: addi    x3, x3, 1           # x03 ++
+fe119ee3 // PC=0x1c line=13: bne     x3, x1, loop_head_bneq
+00000263 // PC=0x20 line=14: beq     x0, x0, trap
diff --git a/src/asm/test/beq.result b/src/asm/test/beq.result
@@ -17,13 +17,13 @@ Ran       10000 cycles, finishing.
 #TESTASSERTOUTPUT|---------------------------------------|
 #TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x01, ra = 0x00000005 (         5)|
-#TESTASSERTOUTPUT|      x02, sp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000005 (         5)|
 #TESTASSERTOUTPUT|      x03, gp = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|      x08, s0 = 0x00000008 (         8)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
@@ -40,7 +40,7 @@ Ran       10000 cycles, finishing.
 #TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|      x25, s9 = 0x00000008 (         8)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|

diff --git a/src/asm/test/bne.result b/src/asm/test/bne.result
@@ -0,0 +1,50 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
+WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/bne.memh): Not enough words in the file for the requested range [0:1023].
+Running simulation of memory ../asm/out/bne.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
+FST info: dumpfile rv32_simulator.fst opened for output.
+Ran       10000 cycles, finishing.
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT| Register File State :)                |
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x01, ra = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x03, gp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x12, a2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x13, a3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x14, a4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x15, a5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x16, a6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x17, a7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x18, s2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x19, s3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x20, s4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x21, s5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|---------------------------------------|
diff --git a/src/asm/test/branch.result b/src/asm/test/branch.result
@@ -0,0 +1,50 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
+WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/branch.memh): Not enough words in the file for the requested range [0:1023].
+Running simulation of memory ../asm/out/branch.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
+FST info: dumpfile rv32_simulator.fst opened for output.
+Ran       10000 cycles, finishing.
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT| Register File State :)                |
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x01, ra = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000005 (         5)|
+#TESTASSERTOUTPUT|      x03, gp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x12, a2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x13, a3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x14, a4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x15, a5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x16, a6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x17, a7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x18, s2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x19, s3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x20, s4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x21, s5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|---------------------------------------|
diff --git a/src/asm/test/irtypes.result b/src/asm/test/irtypes.result
@@ -1,7 +1,17 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
 WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/irtypes.memh): Not enough words in the file for the requested range [0:1023].
-Running simulation of memory ../asm/out/irtypes.memh for up to         100 cycles. Waves will be stored to rv32_simulator.fst.
+Running simulation of memory ../asm/out/irtypes.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
 FST info: dumpfile rv32_simulator.fst opened for output.
-Ran         100 cycles, finishing.
+Ran       10000 cycles, finishing.
 #TESTASSERTOUTPUT|---------------------------------------|
 #TESTASSERTOUTPUT| Register File State :)                |
 #TESTASSERTOUTPUT|---------------------------------------|

diff --git a/src/asm/test/itypes.result b/src/asm/test/itypes.result
@@ -1,7 +1,17 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
 WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/itypes.memh): Not enough words in the file for the requested range [0:1023].
-Running simulation of memory ../asm/out/itypes.memh for up to         100 cycles. Waves will be stored to rv32_simulator.fst.
+Running simulation of memory ../asm/out/itypes.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
 FST info: dumpfile rv32_simulator.fst opened for output.
-Ran         100 cycles, finishing.
+Ran       10000 cycles, finishing.
 #TESTASSERTOUTPUT|---------------------------------------|
 #TESTASSERTOUTPUT| Register File State :)                |
 #TESTASSERTOUTPUT|---------------------------------------|

diff --git a/src/asm/test/storeload.result b/src/asm/test/storeload.result
@@ -1,7 +1,17 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
 WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/storeload.memh): Not enough words in the file for the requested range [0:1023].
-Running simulation of memory ../asm/out/storeload.memh for up to         100 cycles. Waves will be stored to rv32_simulator.fst.
+Running simulation of memory ../asm/out/storeload.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
 FST info: dumpfile rv32_simulator.fst opened for output.
-Ran         100 cycles, finishing.
+Ran       10000 cycles, finishing.
 #TESTASSERTOUTPUT|---------------------------------------|
 #TESTASSERTOUTPUT| Register File State :)                |
 #TESTASSERTOUTPUT|---------------------------------------|

diff --git a/src/components/Makefile b/src/components/Makefile
@@ -105,7 +105,9 @@ rv32_simulator: tests/provided/rv32_simulator.sv src/**/*.sv
 %.validate: %.result
 	node ../asm/validate.js $(basename $<).s test/$< 
 
-test_rv32_all: itypes.validate irtypes.validate storeload.validate beq.validate
+test_rv32_branch: beq.validate bne.validate
+
+test_rv32_all: itypes.validate irtypes.validate storeload.validate test_rv32_branch
 
 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
 # Instruction Type Tests