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MODELSIM/CONVERT_AND_SCALE.v

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+// -------------------------------------------------------------
+// 
+// File Name: hdl_prj\hdlsrc\untitled\CONVERT_AND_SCALE.v
+// Created: 2021-03-05 04:02:09
+// 
+// Generated by MATLAB 9.9 and HDL Coder 3.17
+// 
+// 
+// -- -------------------------------------------------------------
+// -- Rate and Clocking Details
+// -- -------------------------------------------------------------
+// Model base rate: 0.000699301
+// Target subsystem base rate: 0.000699301
+// 
+// 
+// Clock Enable  Sample Time
+// -- -------------------------------------------------------------
+// ce_out        0
+// -- -------------------------------------------------------------
+// 
+// 
+// Output Signal                 Clock Enable  Sample Time
+// -- -------------------------------------------------------------
+// PID_OUT                       ce_out        0
+// -- -------------------------------------------------------------
+// 
+// -------------------------------------------------------------
+
+
+// -------------------------------------------------------------
+// 
+// Module: CONVERT_AND_SCALE
+// Source Path: untitled/CONVERT_AND_SCALE
+// Hierarchy Level: 0
+// 
+// -------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module CONVERT_AND_SCALE
+          (clk,
+           reset_x,
+           clk_enable,
+           In1,
+           In2,
+           ce_out,
+           PID_OUT);
+
+
+  input   clk;
+  input   reset_x;
+  input   clk_enable;
+  input   [4:0] In1;  // ufix5
+  input   [63:0] In2;  // ufix64
+  output  ce_out;
+  output  signed [35:0] PID_OUT;  // sfix36_En14
+
+
+  wire signed [35:0] RECIPROCAL_AND_SCALE_out1;  // sfix36_En14
+  wire signed [36:0] Sum3_sub_cast;  // sfix37_En14
+  wire signed [36:0] Sum3_sub_cast_1;  // sfix37_En14
+  wire signed [36:0] Sum3_out1;  // sfix37_En14
+  wire signed [35:0] Data_Type_Conversion_out1;  // sfix36_En14
+
+
+  RECIPROCAL_AND_SCALE RECIPROCAL_AND_SCALE_1 (.clk(clk),
+                                               .reset_x(reset_x),
+                                               .enb(clk_enable),
+                                               .enb_const_rate(clk_enable),
+                                               .In1(In2),  // ufix64
+                                               .Out1(RECIPROCAL_AND_SCALE_out1)  // sfix36_En14
+                                               );
+
+  assign Sum3_sub_cast = {18'b0, {In1, 14'b00000000000000}};
+  assign Sum3_sub_cast_1 = {RECIPROCAL_AND_SCALE_out1[35], RECIPROCAL_AND_SCALE_out1};
+  assign Sum3_out1 = Sum3_sub_cast - Sum3_sub_cast_1;
+
+
+
+  assign Data_Type_Conversion_out1 = Sum3_out1[35:0];
+
+
+
+  assign PID_OUT = Data_Type_Conversion_out1;
+
+  assign ce_out = clk_enable;
+
+endmodule  // CONVERT_AND_SCALE
+