minor bug fix

gthparch · Feb 27, 2024 · 3bf5a4d · 3bf5a4d
1 parent 4310dcb
commit 3bf5a4d
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Showing 4 changed files with 29 additions and 25 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -1,6 +1,6 @@
 [submodule "internal"]
 	path = internal
-	url = https://github.com/gthparch/macsim_internal
+	url = git@github.com:gthparch/macsim_internal.git
 [submodule "src/rwqueue"]
 	path = src/rwqueue
 	url = https://github.com/cameron314/readerwriterqueue
diff --git a/bin/params.in b/bin/params.in
@@ -1,39 +1,39 @@
 
 # Simulation Configuration
-num_sim_cores 16
-num_sim_small_cores 16
+num_sim_cores 80 
+num_sim_small_cores 80 
 core_type nvbit
-max_threads_per_core 80
+max_threads_per_core 1024 
 num_sim_medium_cores 0
 num_sim_large_cores 0
 
 
 # Clock
 # from device query for gtx580 on damint - gpu clock - 1.66 GHz, mem clock - 2100 MHz
-clock_cpu 4.0
-clock_gpu 4.0
-clock_llc 4.0
-clock_noc 4.0
-clock_mc  4.0
+clock_cpu 2.0
+clock_gpu 2.0
+clock_llc 2.0
+clock_noc 2.0
+clock_mc  2.0
 
 
 # Small Core Configuration
-fetch_wdith 2
+fetch_wdith 4
 width 1
 fetch_latency 5
 alloc_latency 5
 rob_size 1024
 schedule ooo
 isched_rate 4
-msched_rate 2
-fsched_rate 2
+msched_rate 4
+fsched_rate 4
 bp_hist_length 14
-max_block_per_core 4
+max_block_per_core  8  
 fetch_policy rr
 mt_no_fetch_br 1
 fetch_only_load_ready 0
-schedule_ratio 2
-fetch_ratio 2
+schedule_ratio 4
+fetch_ratio 4
 gpu_sched 1
 icache_num_set 8
 
@@ -54,20 +54,24 @@ shared_mem_ports 1
 byte_level_access 0
 
 l1_small_line_size 128
-#48 KB
-l1_small_num_set 64
+#96 KB
+l1_small_num_set 128 
 l1_small_assoc 6
 #16 KB
 #l1_small_num_set 32
 #l1_small_assoc 4
 
-# L3 Cache
-num_llc 6
+l1_small_latency 30
+l2_small_latency 100
+llc_latency 200
+
+# L3 Cache (4.5MB 24 way)
+num_llc 12 
 llc_num_set 128
 llc_line_size 128
-llc_assoc 8
+llc_assoc 24 
 llc_num_bank 4
-llc_latency 10
+llc_latency 200 
 
 
 # DRAM
@@ -94,7 +98,7 @@ bug_detector_enable 1
 sim_cycle_count 0
 max_insts 200000000
 heartbeat_interval 1000000
-forward_progress_limit 50000
+forward_progress_limit 100000
 blocks_to_simulate 0
 ptx_exec_ratio 2
 num_warp_scheduler 2

diff --git a/src/bug_detector.cc b/src/bug_detector.cc
@@ -169,7 +169,7 @@ void bug_detector_c::print(int core_id, int thread_id) {
           << left << (*m_uop_table[ii])[(*I)] << setw(15) << left
           << CYCLE - (*m_uop_table[ii])[(*I)] << setw(25) << left
           << uop_c::g_uop_state_name[uop->m_state] << setw(25) << left
-          << (core_type == "ptx"
+          << ((core_type == "ptx") || (core_type == "nvbit")
                 ? gpu_decoder_c::g_tr_opcode_names[uop->m_opcode]
                 : cpu_decoder_c::g_tr_opcode_names[uop->m_opcode])
           << setw(20) << left << uop_c::g_uop_type_name[uop->m_uop_type]

diff --git a/src/core.cc b/src/core.cc
@@ -377,7 +377,7 @@ void core_c::run_a_cycle(bool pll_lock) {
 
   // to simulate kernel invocation from host code
   if (*KNOB(KNOB_ENABLE_CONDITIONAL_EXECUTION)) {
-    if (m_core_type == "ptx" && m_simBase->m_gpu_paused) {
+    if ((m_core_type == "ptx" || m_core_type == "nvbit") && m_simBase->m_gpu_paused) {
       m_frontend->stop();
     }
   }
@@ -706,7 +706,7 @@ void core_c::train_hw_pref(int level, int tid, Addr addr, Addr pc, uop_c* uop,
 // hardware prefetcher initialization
 void core_c::pref_init(void) {
   if (*m_simBase->m_knobs->KNOB_PREF_FRAMEWORK_ON && m_knob_enable_pref) {
-    m_hw_pref->pref_init(m_core_type == "ptx" ? true : false);
+    m_hw_pref->pref_init((m_core_type == "ptx") || (m_core_type == "nvbit") ? true : false);
   }
 }