Verilog Projects for Digital Circuit Design Lab (EC205)

National Institute of Technology, Warangal

These are codes written by me for my own purpose. I am not responsible for any code copied/taken from this repository.

Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
.github		.github
4BitComparator		4BitComparator
4b Counter		4b Counter
4b UD Counter		4b UD Counter
4bASyncUD		4bASyncUD
8bSBA		8bSBA
8bitripadd		8bitripadd
8x1mux_bool		8x1mux_bool
8x3encoder		8x3encoder
CLA4B		CLA4B
CSA_4B		CSA_4B
Counteer		Counteer
Data_FlipFlop		Data_FlipFlop
FourBRipAdd		FourBRipAdd
FullSubtractor		FullSubtractor
JK_FlipFlop		JK_FlipFlop
KSA16b		KSA16b
KoggeStoneAdder8Bit		KoggeStoneAdder8Bit
Multiplier_Architecture		Multiplier_Architecture
Parity Generator		Parity Generator
RISCVP		RISCVP
SR_Flip_Flop		SR_Flip_Flop
Sequence Detector		Sequence Detector
SequenceDetector		SequenceDetector
SerialInSerialOutBiDirectionalRegister		SerialInSerialOutBiDirectionalRegister
SimplificationOfBooleanExp		SimplificationOfBooleanExp
SixteenTo1Mux		SixteenTo1Mux
TFF		TFF
add_shift_multiplier		add_shift_multiplier
adder_subtractor		adder_subtractor
binary_graycode		binary_graycode
calculator		calculator
decoder 8x3		decoder 8x3
demux1x8		demux1x8
fulladder		fulladder
paritychecker		paritychecker
project_3		project_3
README.MD		README.MD

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