Add support for upduino 2 board

README.md

@@ -58,3 +58,7 @@ https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593
 ### lx9_microboard
 
 https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-s6mb-lx9-g-3074457345628965461/
+
+### Upduino 2
+
+http://www.gnarlygrey.com/

blinky.core

@@ -23,6 +23,11 @@ filesets:
   tinyfpga_bx:
     files: [tinyfpga_bx/pinout.pcf : {file_type : PCF}]
 
+  upduino2:
+    files:
+      - upduino2/blinky_upduino2.v : {file_type : verilogSource}
+      - upduino2/pinout.pcf : {file_type : PCF}
+
 targets:
   default:
     filesets : [rtl]
@@ -72,6 +77,17 @@ targets:
         pnr: next
     toplevel : blinky
 
+  upduino2:
+    default_tool : icestorm
+    filesets : [rtl, proginfo, upduino2]
+    hooks:
+      post_run: [iceprog]
+    tools:
+      icestorm:
+        nextpnr_options : [--up5k]
+        pnr: next
+    toplevel : blinky_upduino2
+
 parameters:
   clk_freq_hz:
     datatype    : int
@@ -83,5 +99,7 @@ parameters:
     paramtype   : vlogparam
 
 scripts:
+  iceprog:
+    cmd : [python, proginfo.py, iceprog]
   tinyprog:
     cmd : [python, proginfo.py, tinyprog]

sw/proginfo.py

@@ -7,3 +7,5 @@
 print("To program the board run:")
 if sys.argv[1] == 'tinyprog':
     print("tinyprog --program {}".format(os.path.join(os.getcwd(), "fusesoc_utils_blinky_0.bin")))
+elif sys.argv[1] == 'iceprog':
+    print("iceprog {}".format(os.path.join(os.getcwd(), "fusesoc_utils_blinky_0.bin")))

upduino2/blinky_upduino2.v

@@ -0,0 +1,45 @@
+module blinky_upduino2
+  (
+   output wire g,
+   output wire b,
+   output wire r);
+
+   wire        clk;
+   wire        q;
+   reg 	       q_r;
+   reg [2:0]   rgb = 3'b001;
+
+   SB_HFOSC inthosc
+     (
+      .CLKHFPU(1'b1),
+      .CLKHFEN(1'b1),
+      .CLKHF(clk));
+
+   SB_RGBA_DRV
+     #(
+       .CURRENT_MODE ("0b1"),
+       .RGB0_CURRENT ("0b000111"),
+       .RGB1_CURRENT ("0b000111"),
+       .RGB2_CURRENT ("0b000111"))
+   RGBA_DRIVER
+     (
+      .CURREN(1'b1),
+      .RGBLEDEN(1'b1),
+      .RGB0PWM(rgb[0] & q),
+      .RGB1PWM(rgb[1] & q),
+      .RGB2PWM(rgb[2] & q),
+      .RGB0(g),
+      .RGB1(b),
+      .RGB2(r));
+
+   always @(posedge clk) begin
+      q_r <= q;
+      if (q & !q_r)
+	rgb <= {rgb[1:0], rgb[2]};
+   end
+
+   blinky #(.clk_freq_hz (48_000_000)) blinky
+     (.clk (clk),
+      .q   (q));
+
+endmodule

upduino2/pinout.pcf

@@ -0,0 +1,3 @@
+set_io g 39
+set_io b 40
+set_io r 41