Added support for Nexys Video FPGA (#17)

Added support for Nexys Video FPGA
fusesoc · Feb 24, 2020 · 68e193d · 68e193d
1 parent 4a0c7e1
commit 68e193d
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diff --git a/README.md b/README.md
@@ -83,6 +83,10 @@ https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-s6mb-lx9-g
 
 https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum
 
+### nexys_video
+
+https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start
+
 ### opos6ul_sp
 
 http://www.armadeus.org/wiki/index.php?title=OPOS6UL_SP

diff --git a/blinky.core b/blinky.core
@@ -55,6 +55,8 @@ filesets:
 
   nexys_a7: {files: [nexys_a7/blinky.xdc : {file_type : xdc}]}
 
+  nexys_video: {files: [nexys_video/blinky.xdc : {file_type : xdc}]}
+
   opos6ul_sp:
     files: [opos6ul_sp/blinky.ucf : {file_type : UCF}]
 
@@ -239,6 +241,15 @@ targets:
         part : xc7a100tcsg324-1
     toplevel : blinky
 
+    nexys_video:
+    default_tool: vivado
+    filesets : [rtl, nexys_video]
+    parameters : [clk_freq_hz=100000000]
+    tools:
+      vivado:
+        part : xc7a200tsbg484-1
+    toplevel : blinky
+
   opos6ul_sp:
     default_tool : ise
     filesets : [rtl, opos6ul_sp]

diff --git a/nexys_video/blinky.xdc b/nexys_video/blinky.xdc
@@ -0,0 +1,6 @@
+## Clock Signal
+set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+
+## LED
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { q }]; #IO_L15P_T2_DQS_13 Sch=led[0]