Add DE5-Net support

Add the Terasic DE5-Net Stratix V board.
fusesoc · Sep 28, 2020 · 5c28faf · 5c28faf
1 parent 6781d3d
commit 5c28faf
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Showing 3 changed files with 37 additions and 1 deletion.
diff --git a/blinky.core b/blinky.core
@@ -16,7 +16,7 @@ filesets:
       - apf27/options.tcl : {file_type : tclSource}
 
   apf51:
-    files: 
+    files:
       - apf51/blinky.ucf : {file_type : UCF}
       - apf51/options.tcl : {file_type : tclSource}
 
@@ -52,6 +52,11 @@ filesets:
       - de0_nanosoc/de0_nanosoc.sdc  : {file_type : SDC}
       - de0_nanosoc/pinmap.tcl       : {file_type : tclSource}
 
+  de5_net:
+    files:
+      - de5_net/de5_net.sdc : {file_type : SDC}
+      - de5_net/pinmap.tcl  : {file_type: tclSource}
+
   de10_soc:
     files:
       - de10_soc/de10_soc.sdc : {file_type : SDC}
@@ -322,6 +327,16 @@ targets:
         board_device_index : 2
     toplevel: blinky
 
+  de5_net:
+    default_tool : quartus
+    filesets : [rtl, de5_net]
+    parameters : [clk_freq_hz=50000000]
+    tools:
+      quartus:
+        family : Stratix V
+        device : 5SGXEA7N2F45C2
+    toplevel: blinky
+
   ecp5_evn:
     default_tool : trellis
     description : ECP5 Evaluation Board

diff --git a/de5_net/de5_net.sdc b/de5_net/de5_net.sdc
@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
diff --git a/de5_net/pinmap.tcl b/de5_net/pinmap.tcl
@@ -0,0 +1,13 @@
+#
+# Clock / Reset
+#
+set_location_assignment PIN_AW35 -to clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk
+
+#
+# GPIO0 - board name LED_BRACKET[0]
+#
+set_location_assignment PIN_AH15 -to q
+set_instance_assignment -name IO_STANDARD "2.5 V" -to q
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to q
+set_instance_assignment -name SLEW_RATE 1 -to q