Added support for board "zrtech v2.00"

blinky.core

@@ -48,6 +48,11 @@ filesets:
       - upduino2/blinky_upduino2.v : {file_type : verilogSource}
       - upduino2/pinout.pcf : {file_type : PCF}
 
+  zrtech_v2:
+    files:
+      - zrtech_v2/zrtech_v2.sdc : {file_type : SDC}
+      - zrtech_v2/pinmap.tcl    : {file_type: tclSource}
+
 targets:
   default: &default
     filesets : [rtl]
@@ -161,6 +166,16 @@ targets:
         pnr: next
     toplevel : blinky_upduino2
 
+  zrtech_v2:
+    default_tool : quartus
+    filesets : [rtl, zrtech_v2]
+    parameters : [clk_freq_hz=50000000]
+    tools:
+      quartus:
+        family : Cyclone IV E
+        device : EP4CE6E22C8
+    toplevel: blinky
+
 parameters:
   clk_freq_hz:
     datatype    : int

zrtech_v2/pinmap.tcl

@@ -0,0 +1,11 @@
+#
+# Clock
+#
+set_location_assignment PIN_24 -to clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
+
+#
+# LED D2 (DS_DP)
+#
+set_location_assignment PIN_3 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q

zrtech_v2/zrtech_v2.sdc

@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty