Add OrangeCrab R0.2 target

Add support for OrangeCrab R0.2
fusesoc · Jul 25, 2020 · 4ff8c62 · 4ff8c62
1 parent b64971d
commit 4ff8c62
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Showing 4 changed files with 51 additions and 0 deletions.
diff --git a/blinky.core b/blinky.core
@@ -95,6 +95,11 @@ filesets:
   opos6ul_sp:
     files: [opos6ul_sp/blinky.ucf : {file_type : UCF}]
 
+  orangecrab:
+    files:
+      - orangecrab/orangecrab_r02.lpf : {file_type : LPF}
+      - orangecrab/blinky_orangecrab.v : {file_type : verilogSource}
+
   pipistrello:
     files: [pipistrello/blinky.ucf : {file_type : UCF}]
 
@@ -403,6 +408,17 @@ targets:
         speed   : -2
     toplevel : blinky
 
+  orangecrab_r0.2: &orangecrab
+    default_tool : trellis
+    description : OrangeCrab R0.2
+    filesets : [rtl, proginfo, orangecrab]
+    hooks:
+      post_run: [dfu-util]
+    tools:
+      trellis:
+        nextpnr_options : [--package, CSFBGA285, --25k]
+    toplevel : blinky_orangecrab
+
   pipistrello:
     default_tool : ise
     filesets : [rtl, pipistrello]
@@ -561,3 +577,5 @@ scripts:
     cmd : [python3, proginfo.py, tinyprog]
   ujprog:
     cmd : [python3, proginfo.py, ujprog]
+  dfu-util:
+    cmd : [python3, proginfo.py, dfu-util]
diff --git a/orangecrab/blinky_orangecrab.v b/orangecrab/blinky_orangecrab.v
@@ -0,0 +1,17 @@
+module blinky_orangecrab
+  (input wire 	    clk,
+   input wire       btn,
+   output wire 	    r,
+   output wire 	    g,
+   output wire 	    b,
+   );
+
+
+   blinky #(.clk_freq_hz (48_000_000)) blinky
+     (.clk (clk),
+      .q   (q));
+
+    assign r = ~q;
+    assign g = ~q;
+    assign b = ~q;
+endmodule
diff --git a/orangecrab/orangecrab_r02.lpf b/orangecrab/orangecrab_r02.lpf
@@ -0,0 +1,14 @@
+LOCATE COMP "clk" SITE "A9";
+IOBUF  PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 48 MHZ;
+
+LOCATE COMP "r" SITE "K4";
+LOCATE COMP "g" SITE "M3";
+LOCATE COMP "b" SITE "J3";
+
+IOBUF PORT "r" IO_TYPE=LVCMOS33;
+IOBUF PORT "g" IO_TYPE=LVCMOS33;
+IOBUF PORT "b" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "btn" SITE "J17";  # BTN_PWRn (inverted logic)
+IOBUF PORT "btn" PULLMODE=UP IO_TYPE=LVCMOS33;
diff --git a/sw/proginfo.py b/sw/proginfo.py
@@ -13,3 +13,5 @@
 elif sys.argv[1] == 'ujprog':
     print("ujprog {}".format(os.path.join(os.getcwd(), "Implementation0", system_name+"_Implementation0.bit")))
     print("Other programming options are listed here https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md#programming-options")
+elif sys.argv[1] == 'dfu-util':
+    print("dfu-util -d 1209:5af0 -D {}".format(os.path.join(os.getcwd(), system_name+".bit")))