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8bit_divider_sim
8bit_divider_sim PublicThis example implements a digital 8-bit sequential divider simulation on SimulIDE
AngelScript
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kdheepak/quarto-svgbob
kdheepak/quarto-svgbob PublicRender svgbob diagrams directly in your quarto documents.
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veri2sim
veri2sim PublicThis is a simple Verilog to SimulIDE block converter written in Python using the PLY module.
Python
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