litedram/frontend/adapter.py rewrite up converter to optimize for ban…

…dwidth

This change is necessary to run litevideo, as old up converter was too slow to support
high bandwidth requirements of HDMI core.
Also old upconverter had two bugs:
* reading sequentially and non-sequentially would return data in the same order
* writing sequentailly and non-sequentially would return different memory state

test/test_adapter.py add new up converter test: test_up_converter_writes_not_sequential
This test checks if non-sequential writes to one dram word will create the same result as sequential writes
Add parameters for rx_buffer, tx_buffer and cmd_buffer depths

Signed-off-by: Maciej Dudek <[email protected]>

litedram/core/crossbar.py

@@ -76,7 +76,8 @@ def __init__(self, controller):
 
         self.masters = []
 
-    def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False):
+    def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=False,
+            rx_buffer_depth=4, tx_buffer_depth=4, cmd_buffer_depth=4, priority=0):
         if self.finalized:
             raise FinalizeError
 
@@ -117,7 +118,8 @@ def get_port(self, mode="both", data_width=None, clock_domain="sys", reverse=Fal
                 clock_domain  = clock_domain,
                 id            = port.id)
             self.submodules += ClockDomainsRenamer(clock_domain)(
-                LiteDRAMNativePortConverter(new_port, port, reverse))
+                LiteDRAMNativePortConverter(new_port, port, reverse,
+                    rx_buffer_depth, tx_buffer_depth, cmd_buffer_depth))
             port = new_port
 
         return port