Generated from stm32-data 91fc4f2066905e57d6a501d7bd6c7b15a982d342

embassy-rs · Jan 9, 2025 · c583333 · c583333
1 parent 609684a
commit c583333
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Showing 3 changed files with 7 additions and 7 deletions.
diff --git a/data/registers/adc_v4.json b/data/registers/adc_v4.json
@@ -770,7 +770,7 @@
         "bit_size": 5
       },
       {
-        "name": "EXTEN",
+        "name": "JEXTEN",
         "description": "group injected external trigger polarity",
         "bit_offset": 7,
         "bit_size": 2,

diff --git a/stm32-metapac/src/peripherals/adc_v4.rs b/stm32-metapac/src/peripherals/adc_v4.rs
@@ -1865,13 +1865,13 @@ pub mod regs {
         }
         #[doc = "group injected external trigger polarity"]
         #[inline(always)]
-        pub const fn exten(&self) -> super::vals::Exten {
+        pub const fn jexten(&self) -> super::vals::Exten {
             let val = (self.0 >> 7usize) & 0x03;
             super::vals::Exten::from_bits(val as u8)
         }
         #[doc = "group injected external trigger polarity"]
         #[inline(always)]
-        pub fn set_exten(&mut self, val: super::vals::Exten) {
+        pub fn set_jexten(&mut self, val: super::vals::Exten) {
             self.0 = (self.0 & !(0x03 << 7usize)) | (((val.to_bits() as u32) & 0x03) << 7usize);
         }
         #[doc = "group injected sequencer rank 1-4"]
@@ -1901,7 +1901,7 @@ pub mod regs {
             f.debug_struct("Jsqr")
                 .field("jl", &self.jl())
                 .field("jextsel", &self.jextsel())
-                .field("exten", &self.exten())
+                .field("jexten", &self.jexten())
                 .field(
                     "jsq",
                     &[self.jsq(0usize), self.jsq(1usize), self.jsq(2usize), self.jsq(3usize)],
@@ -1916,13 +1916,13 @@ pub mod regs {
             struct Jsqr {
                 jl: u8,
                 jextsel: u8,
-                exten: super::vals::Exten,
+                jexten: super::vals::Exten,
                 jsq: [u8; 4usize],
             }
             let proxy = Jsqr {
                 jl: self.jl(),
                 jextsel: self.jextsel(),
-                exten: self.exten(),
+                jexten: self.jexten(),
                 jsq: [self.jsq(0usize), self.jsq(1usize), self.jsq(2usize), self.jsq(3usize)],
             };
             defmt::write!(f, "{}", proxy)

diff --git a/stm32-metapac/src/registers/adc_v4.rs b/stm32-metapac/src/registers/adc_v4.rs
@@ -1060,7 +1060,7 @@ pub(crate) static REGISTERS: IR = IR {
                     enumm: None,
                 },
                 Field {
-                    name: "exten",
+                    name: "jexten",
                     description: Some("group injected external trigger polarity"),
                     bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                     bit_size: 2,