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Generated from stm32-data 6d786292679c8c80f95a69167cc19787c6010194
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Embassy CI committed Feb 2, 2025
1 parent c036b50 commit 7c3bd7c
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Showing 9 changed files with 147 additions and 0 deletions.
10 changes: 10 additions & 0 deletions data/registers/rtc_v3.json
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Original file line number Diff line number Diff line change
Expand Up @@ -528,6 +528,16 @@
"fieldset/ICSR": {
"description": "Initialization control and status register",
"fields": [
{
"name": "ALRWF",
"description": "Alarm write enabled",
"bit_offset": 0,
"bit_size": 1,
"array": {
"len": 2,
"stride": 1
}
},
{
"name": "WUTWF",
"description": "Wakeup timer write enabled",
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10 changes: 10 additions & 0 deletions data/registers/rtc_v3l5.json
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Original file line number Diff line number Diff line change
Expand Up @@ -512,6 +512,16 @@
"fieldset/ICSR": {
"description": "Initialization control and status register",
"fields": [
{
"name": "ALRWF",
"description": "Alarm write enabled",
"bit_offset": 0,
"bit_size": 1,
"array": {
"len": 2,
"stride": 1
}
},
{
"name": "WUTWF",
"description": "Wakeup timer write flag",
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10 changes: 10 additions & 0 deletions data/registers/rtc_v3u5.json
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Original file line number Diff line number Diff line change
Expand Up @@ -557,6 +557,16 @@
"fieldset/ICSR": {
"description": "Initialization control and status register",
"fields": [
{
"name": "ALRWF",
"description": "Alarm write enabled",
"bit_offset": 0,
"bit_size": 1,
"array": {
"len": 2,
"stride": 1
}
},
{
"name": "WUTWF",
"description": "Wakeup timer write enabled",
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18 changes: 18 additions & 0 deletions stm32-metapac/src/peripherals/rtc_v3.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1072,6 +1072,21 @@ pub mod regs {
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icsr(pub u32);
impl Icsr {
#[doc = "Alarm write enabled"]
#[inline(always)]
pub const fn alrwf(&self, n: usize) -> bool {
assert!(n < 2usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Alarm write enabled"]
#[inline(always)]
pub fn set_alrwf(&mut self, n: usize, val: bool) {
assert!(n < 2usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Wakeup timer write enabled"]
#[inline(always)]
pub const fn wutwf(&self) -> bool {
Expand Down Expand Up @@ -1181,6 +1196,7 @@ pub mod regs {
impl core::fmt::Debug for Icsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icsr")
.field("alrwf", &[self.alrwf(0usize), self.alrwf(1usize)])
.field("wutwf", &self.wutwf())
.field("shpf", &self.shpf())
.field("inits", &self.inits())
Expand All @@ -1198,6 +1214,7 @@ pub mod regs {
fn format(&self, f: defmt::Formatter) {
#[derive(defmt :: Format)]
struct Icsr {
alrwf: [bool; 2usize],
wutwf: bool,
shpf: bool,
inits: bool,
Expand All @@ -1209,6 +1226,7 @@ pub mod regs {
recalpf: super::vals::Recalpf,
}
let proxy = Icsr {
alrwf: [self.alrwf(0usize), self.alrwf(1usize)],
wutwf: self.wutwf(),
shpf: self.shpf(),
inits: self.inits(),
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18 changes: 18 additions & 0 deletions stm32-metapac/src/peripherals/rtc_v3l5.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1013,6 +1013,21 @@ pub mod regs {
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icsr(pub u32);
impl Icsr {
#[doc = "Alarm write enabled"]
#[inline(always)]
pub const fn alrwf(&self, n: usize) -> bool {
assert!(n < 2usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Alarm write enabled"]
#[inline(always)]
pub fn set_alrwf(&mut self, n: usize, val: bool) {
assert!(n < 2usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Wakeup timer write flag"]
#[inline(always)]
pub const fn wutwf(&self) -> bool {
Expand Down Expand Up @@ -1100,6 +1115,7 @@ pub mod regs {
impl core::fmt::Debug for Icsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icsr")
.field("alrwf", &[self.alrwf(0usize), self.alrwf(1usize)])
.field("wutwf", &self.wutwf())
.field("shpf", &self.shpf())
.field("inits", &self.inits())
Expand All @@ -1115,6 +1131,7 @@ pub mod regs {
fn format(&self, f: defmt::Formatter) {
#[derive(defmt :: Format)]
struct Icsr {
alrwf: [bool; 2usize],
wutwf: bool,
shpf: bool,
inits: bool,
Expand All @@ -1124,6 +1141,7 @@ pub mod regs {
recalpf: super::vals::Recalpf,
}
let proxy = Icsr {
alrwf: [self.alrwf(0usize), self.alrwf(1usize)],
wutwf: self.wutwf(),
shpf: self.shpf(),
inits: self.inits(),
Expand Down
18 changes: 18 additions & 0 deletions stm32-metapac/src/peripherals/rtc_v3u5.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1105,6 +1105,21 @@ pub mod regs {
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icsr(pub u32);
impl Icsr {
#[doc = "Alarm write enabled"]
#[inline(always)]
pub const fn alrwf(&self, n: usize) -> bool {
assert!(n < 2usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Alarm write enabled"]
#[inline(always)]
pub fn set_alrwf(&mut self, n: usize, val: bool) {
assert!(n < 2usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Wakeup timer write enabled"]
#[inline(always)]
pub const fn wutwf(&self) -> bool {
Expand Down Expand Up @@ -1214,6 +1229,7 @@ pub mod regs {
impl core::fmt::Debug for Icsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icsr")
.field("alrwf", &[self.alrwf(0usize), self.alrwf(1usize)])
.field("wutwf", &self.wutwf())
.field("shpf", &self.shpf())
.field("inits", &self.inits())
Expand All @@ -1231,6 +1247,7 @@ pub mod regs {
fn format(&self, f: defmt::Formatter) {
#[derive(defmt :: Format)]
struct Icsr {
alrwf: [bool; 2usize],
wutwf: bool,
shpf: bool,
inits: bool,
Expand All @@ -1242,6 +1259,7 @@ pub mod regs {
recalpf: super::vals::Recalpf,
}
let proxy = Icsr {
alrwf: [self.alrwf(0usize), self.alrwf(1usize)],
wutwf: self.wutwf(),
shpf: self.shpf(),
inits: self.inits(),
Expand Down
21 changes: 21 additions & 0 deletions stm32-metapac/src/registers/rtc_v3.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1245,6 +1245,27 @@ pub(crate) static REGISTERS: IR = IR {
),
bit_size: 32,
fields: &[
Field {
name: "alrwf",
description: Some(
"Alarm write enabled",
),
bit_offset: BitOffset::Regular(
RegularBitOffset {
offset: 0,
},
),
bit_size: 1,
array: Some(
Array::Regular(
RegularArray {
len: 2,
stride: 1,
},
),
),
enumm: None,
},
Field {
name: "wutwf",
description: Some(
Expand Down
21 changes: 21 additions & 0 deletions stm32-metapac/src/registers/rtc_v3l5.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1216,6 +1216,27 @@ pub(crate) static REGISTERS: IR = IR {
),
bit_size: 32,
fields: &[
Field {
name: "alrwf",
description: Some(
"Alarm write enabled",
),
bit_offset: BitOffset::Regular(
RegularBitOffset {
offset: 0,
},
),
bit_size: 1,
array: Some(
Array::Regular(
RegularArray {
len: 2,
stride: 1,
},
),
),
enumm: None,
},
Field {
name: "wutwf",
description: Some(
Expand Down
21 changes: 21 additions & 0 deletions stm32-metapac/src/registers/rtc_v3u5.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1317,6 +1317,27 @@ pub(crate) static REGISTERS: IR = IR {
),
bit_size: 32,
fields: &[
Field {
name: "alrwf",
description: Some(
"Alarm write enabled",
),
bit_offset: BitOffset::Regular(
RegularBitOffset {
offset: 0,
},
),
bit_size: 1,
array: Some(
Array::Regular(
RegularArray {
len: 2,
stride: 1,
},
),
),
enumm: None,
},
Field {
name: "wutwf",
description: Some(
Expand Down

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