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Correct user_id bit order in gl verilog and layout. #518

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merged 2 commits into from
Jan 10, 2024
Merged

Correct user_id bit order in gl verilog and layout. #518

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092ff66
Correct user_id bit order in gl verilog and layout.
d-m-bailey Dec 6, 2023
fad93a0
Apply automatic changes to Manifest and README.rst
d-m-bailey Dec 6, 2023
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2 changes: 1 addition & 1 deletion manifest
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,6 @@ b53c154e6acaf44e858c936c8027d0229608676e verilog/rtl/pads.v
b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
9178c87e3d5196fd3e6abae6fc310e1b663ade0e verilog/rtl/toplevel_cocotb.v
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py
b8b8dd779cbf6f2583188d2b92feddddfef4847f scripts/set_user_id.py
731116709a44d13225170acc83cd34ff9e00fa39 scripts/generate_fill.py
dff8adfb05bedf96f86e16a18ce3cd5818d6fb78 scripts/compositor.py
4 changes: 2 additions & 2 deletions scripts/set_user_id.py
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Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,7 @@ def usage():
# Convert to binary
try:
user_id_int = int('0x' + user_id_value, 0)
user_id_bits = '{0:032b}'.format(user_id_int)
user_id_bits = '{0:032b}'.format(user_id_int)[::-1]
except:
user_project_path = arguments[0]

Expand Down Expand Up @@ -170,7 +170,7 @@ def usage():

try:
user_id_int = int('0x' + user_id_value, 0)
user_id_bits = '{0:032b}'.format(user_id_int)
user_id_bits = '{0:032b}'.format(user_id_int)[::-1]
except:
print('Error: Cannot parse user ID "' + user_id_value + '" as an 8-digit hex number.')
sys.exit(1)
Expand Down