Verilog: use zero_extend_exprt

This replaces two typecasts by zero_extend_exprt.

src/verilog/verilog_typecheck_expr.cpp

@@ -2097,23 +2097,14 @@ Function: zero_extend
 
 static exprt zero_extend(const exprt &expr, const typet &type)
 {
-  auto old_width = expr.type().id() == ID_bool ? 1
-                   : expr.type().id() == ID_integer
-                     ? 32
-                     : to_bitvector_type(expr.type()).get_width();
-
-  // first make unsigned
-  typet tmp_type;
-
-  if(type.id() == ID_unsignedbv)
-    tmp_type = unsignedbv_typet{old_width};
-  else if(type.id() == ID_verilog_unsignedbv)
-    tmp_type = verilog_unsignedbv_typet{old_width};
-  else
-    PRECONDITION(false);
+  exprt result = expr;
+
+  if(expr.type().id() == ID_bool)
+    result = typecast_exprt{expr, unsignedbv_typet{1}};
+  else if(expr.type().id() == ID_integer)
+    result = typecast_exprt{expr, unsignedbv_typet{32}};
 
-  return typecast_exprt::conditional_cast(
-    typecast_exprt::conditional_cast(expr, tmp_type), type);
+  return zero_extend_exprt{std::move(result), type};
 }
 
 /*******************************************************************\