Fix SV formatting

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hw/int/add/full_adder.sv

@@ -12,7 +12,7 @@
 // Delay: O(1)
 
 module full_adder (
-  input  logic  x,    // First operand
+  input  logic x,    // First operand
   input  logic y,    // Second operand
   input  logic cin,  // Carry-in bit
   output logic s,    // Output sum