Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

List of awesome semiconductor startups

Unified Access Page for the TRISTAN project

Port of OpenAI's Whisper model in C/C++

End-to-End Speech Processing Toolkit

A robust, efficient, low-latency speech-to-text library with advanced voice activity detection, wake word activation and instant transcription.

Attention is all you need implementation

List of awesome open source hardware tools

A SystemC productivity library: https://minres.github.io/SystemC-Components/

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

SystemC/TLM-2.0 Co-simulation framework

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

RISC-V Packed SIMD Extension

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor

RISC-V Instruction Set Manual

A matrix extension proposal for AI applications under RISC-V architecture

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

An abstraction library for interfacing EDA tools

Package manager and build abstraction tool for FPGA/ASIC development

RISC-V Cores, SoC platforms and SoCs