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Add EM_RISCV constant #71
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@@ -436,6 +437,7 @@ def self.mapping(val) | |||
when EM_IA_64 then 'Intel IA-64' | |||
when EM_AARCH64 then 'AArch64' | |||
when EM_X86_64 then 'Advanced Micro Devices X86-64' | |||
when EM_RISCV then 'RISC-V' |
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need to enhance the tests to cover this line
Thanks for the PR! Only one feedback that I want the coverage be kept as 100%, please enhance the tests to cover the new line. |
Thanks for the feedback. Sure, no problem, I'll update the PR soon. |
@david942j it took me ages to add unit tests to this PR but hey, such is life. My only concern at the moment it's that I added a binary (it's just a hello world) riscv64 file to the repo without a clear way how to build it. I could update the Makefile to add a cross-compiler in similar way to what is done here: https://github.com/popovicu/risc-v-bare-metal-fake-bios/blob/main/Makefile But then this small library would be depending on the whole riscv64 toolchain and I don't think that's the right path. |
How about adding a Dockerfile that could include all needed toolchain? |
I like that idea, do you have an example of another ruby gem shipping a Dockerfile? |
You don't need a Ruby gem, just provide a Dockerfile under spec/files along with a README to describe the sequence of commands to generate the riscv binary (i.e. docker build; docker run... docker exec gcc ...). The Dockerfile can be based on the latest Ubuntu image and install required cross compiler. As long as I can follow the README you provided to generate the same binary it's good enough :) |
Hi folks,
I was working with some RISC-V ELF binaries and I thought it would be convenient to have them properly recognised by this library so I'm submitting a small change to improve RISC-V architecture support.
Thanks.
References:
https://www.sco.com/developers/gabi/latest/ch4.eheader.html
bminor/glibc@94e73c9
https://www.google.com/search?q=EM_RISCV